[M] Change in flashrom[main]: Add Idaville platform into chipset enable list and add update IRC reg...

[Kevin Yu (Code Review)]

Attention is currently required from: Anastasia Klimchuk, Angel Pons, David Hendricks.

Kevin Yu has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/79340?usp=email )

Change subject: Add Idaville platform into chipset enable list and add update IRC region support
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Patch Set 6:

(1 comment)

Patchset:

PS6:
> Hi Anastasia […]
> Hi Anastasia

Reference documentation
618610_Intel_Xeon_Processor_Family_D-2700_EDSVol_1_Rev2p0.pdf - Section 41.1.6 Firmware Components
631913_Xeon_D-1700_2700_SPI_PG_Rev2_0.pdf - Section 4.3 Region Access Control
intel-sps-5-0-me-bios-interface-575642-rev1-8.pdf - 4.15.2.9 Dual iRC Update Support

iRC – Intelligent Reset Controller
iRC is a regional firmware for the Intel BIOS Firmware for Mehlow, Idaville and Jacobsville platforms.
iRC is stored in Region 13 which is split in two even sections: active image and backup image. On startup higher version is chosen to by applied.
This means that the status of the two region is not fixed. The higher version area will become the active image and the other region will become the backup image.
 
According to #631913 SPI programming guide and ME 5.0 spec description, in addition to giving Region 13 read and write permissions, updating iRC must also unlock iRC through Host ME Region Flash Protection Override (HMRFPO) HECI commands, otherwise iRC will not be writable.
According to iRC Update Flow, the HMRFPO command will only unlock the backup image and can only update the backup image each time. The active image cannot be written.
So for iRC, the submitted changes are divided into the following two parts:
1. Trigger HMRFPO command before updating iRC. HMRFPO command needs to be executed by BIOS Firmware, and flashrom needs to cooperate with BIOS to trigger the command to unlock before updating.
2. Skip errors caused by active image writing failure and continue updating other regions. Since the active image is not writable, during the erasing, writing and verification processes, an error will occur in the active image, causing the flashrom to end its operation.

The revised commit has put the changes to the erase and write parts into ich_hwseq_wait_for_cycle_complete() of ichspi.c.
But the changes to the validation part are still in flashrom.c's compare_range(), which doesn't seem to be transferable to ichspi.c.

Thanks
KevinYu



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Gerrit-Project: flashrom
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Gerrit-Change-Id: Icc526b22a9efc8071e972bb1d8cfc51d6a83651b
Gerrit-Change-Number: 79340
Gerrit-PatchSet: 6
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