[S] Change in flashrom[master]: jedec.c: Move probe_timings decode into sep func

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has submitted this change. ( https://review.coreboot.org/c/flashrom/+/72609 )

(

4 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: jedec.c: Move probe_timings decode into sep func
......................................................................

jedec.c: Move probe_timings decode into sep func

The chip data structure packed from the flashchips db
should have the probe_timing field decoded by its own
function.

Change-Id: I638518cd537954172eb774f6d15af0db7e06d1ba
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/72609
Reviewed-by: Stefan Reinauer 
Tested-by: build bot (Jenkins) 
---
M jedec.c
1 file changed, 36 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Stefan Reinauer: Looks good to me, approved

diff --git a/jedec.c b/jedec.c
index 1ba7b63..6ae767a 100644
--- a/jedec.c
+++ b/jedec.c
@@ -167,6 +167,24 @@
    return 1;
 }

+static int probe_timings(const struct flashchip *chip, unsigned int *tenter, unsigned int *texit)
+{
+	if (chip->probe_timing > 0) {
+		*tenter = *texit = chip->probe_timing;
+	} else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
+		*tenter = *texit = 0;
+	} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
+		msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
+		*tenter = 10000;
+		*texit = 40;
+	} else {
+		msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int probe_jedec(struct flashctx *flash)
 {
    const chipaddr bios = flash->virtual_memory;
@@ -178,18 +196,8 @@
    uint32_t flashcontent1, flashcontent2;
    unsigned int probe_timing_enter, probe_timing_exit;

-	if (chip->probe_timing > 0)
-		probe_timing_enter = probe_timing_exit = chip->probe_timing;
-	else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
-		probe_timing_enter = probe_timing_exit = 0;
-	} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
-		msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
-		probe_timing_enter = 10000;
-		probe_timing_exit = 40;
-	} else {
-		msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
+	if (probe_timings(chip, &probe_timing_enter, &probe_timing_exit) < 0)
    	return 0;
-	}

/* Earlier probes might have been too fast for the chip to enter ID
     * mode completely. Allow the chip to finish this before seeing a