Change in flashrom[master]: ichspi: Define `Write Enable Type (WET)` register under HSFC

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 )

Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
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Patch Set 6:

(1 comment)

File ichspi.c:

https://review.coreboot.org/c/flashrom/+/62888/comment/342c320b_90b7ec42 
PS6, Line 91: /* New HSFC Control bit */
> If you have doubts that the bit was introduced with PCH100, you can always
> test the hardware.

Do we have any action item here regarding the open comment or we are good here ?

Ref to Intel doc 355845 section 22.1.3. Bit 7:3 are reserved, so, WET bit does exist there.

Although there is no use of this bit hence, I will keep this CL aside.