Change in flashrom[master]: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq

[Subrata Banik (Code Review)]

Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Angel Pons, Sridhar Siricilla, Alex Levin, YH Lin, Nico Huber, Martin Roth, Caveh Jalali, David Hendricks, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )

Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
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Patch Set 13:

(2 comments)

Commit Message:

https://review.coreboot.org/c/flashrom/+/61854/comment/53800e7d_3c5ef805 
PS7, Line 17: Without this synchronisation being implemented, flashrom is running
            : into below error:
            : 
            : Erasing and writing flash chip... Timeout error between offset
            : 0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
            : Uh oh. Erase/write failed. Checking if anything has changed.
> > > > Please let me know if anything we need to help for moving this CL?
> > >
> > > What was said in the first message of the comment thread.
> >
> > I have reattempted to update the commit msg with setup details and replication steps.
> >
> > Please suggest if you need better wordings.
>
> Ping!

Ping!

https://review.coreboot.org/c/flashrom/+/61854/comment/c92fbac5_a48a3a68 
PS7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
> > > > Please let me know if anything we need to help for moving this CL?
> > >
> > > What was said in the first message of the comment thread.
> >
> > I'm able to verify this change on eve device. Updated the same in the commit msg.
>
> Ping!

Ping!