Change in flashrom[master]: ichspi: Unify timeouts across all SPI operations to 30s

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Nico Huber, Paul Menzel, Edward O'Callaghan, Anastasia Klimchuk.
Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/62867

to look at the new patch set (#10).

Change subject: ichspi: Unify timeouts across all SPI operations to 30s
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ichspi: Unify timeouts across all SPI operations to 30s

`ich_hwseq_wait_for_cycle_complete()` drops taking `timeout` as argument
in favor of a fixed timeout of `30 seconds` for any given SPI operation
as recommended by the SPI programming guide.

Document: Alder Lake-P Client Platform SPI Programming Guide
          Rev 1.30 (supporting document for multi-master accessing the
                    SPI Flash device.)

Refer to below section to understand the problem in more detail and SPI
operation timeout recommendation from Intel in multi-master
scenarios.

On Intel Chipsets that support multi-mastering access of the SPI flash
may run into a timeout failure when the operation initiated from a
single master just follows the SPI operational timeout recommendation
as per the vendor datasheet (example: winbond spiflash W25Q256JV-DTR
specification, table 9.7).

In the multi-master SPI accessing scenario using hardware sequencing
operation, it's impossible to know the actual status of the SPI bus
prior to individual master starting the operation (SPI Cycle In Progress
a.k.a SCIP bit represents the status of SPI operation on individual
master).

Thus, any SPI operation triggered in multi-master environment might need
to account a worst case scenario where the most time consuming operation
might have occupied the SPI bus from a master and an operation initiated
by another master just timed out.

Here is the timeout calculation for any hardware sequencing operation:
  Worst Case Operational Delay =
        (Maximum Time consumed by a SPI operation + Any marginal
                     adjustment)

Timeout Recommendation for Hardware Sequencing Operation =
        ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +
                        Current Operational latency)

Assume, on Intel platform with 2 SPI master like, Host CPU and CSE, the
Timeout Calculation for SPI Write Operation would look like as below:

Maximum Time consumed by a SPI Operation =  2 seconds
        	(for SPI Erase Operation as per Winbond Data Sheet)

Worst Case Operational Delay = (2 seconds + 50 milliseconds) =
                                   2 seconds 50 milliseconds
  Timeout Recommendation for Hardware Seq Operation =
             (2 seconds 50 milliseconds) * (2 - 1) + 15 milliseconds
                     (for SPI Write Operation as per Winbond Data Sheet)
                        = 2 seconds 65 milliseconds

The timeout value for SPI Hardware Sequencing is defined here based on
the maximum number of master with SPI flash access and worst case SPI
operation time. For example: SPI programming guide on PCH 600 series
defines 5 master sections as HOST CPU/BIOS, CSE, GBE, EC and one reserved.

A rough calculation for the worst case operation a.k.a SPI erase might
take ~5 seconds, hence, the safest timeout value might be
(5 * ~5sec) + 5sec (keeping some buffer) = 30 seconds.

BUG=b:223630977
TEST=Able to perform read/write/erase operation on PCH 600 series
chipset (board name: Brya).

Signed-off-by: Subrata Banik 
Change-Id: Ifa910dea794175d8ee2ad277549e5a0d69cba45b
---
M ichspi.c
1 file changed, 9 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/62867/10