Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18936 )
Change subject: fixup! flashrom: Add Skylake platform support ......................................................................
fixup! flashrom: Add Skylake platform support
Clean up register redefinitions
Change-Id: If122368e852d83f0b04d58840ee3bbeccec1e36b Signed-off-by: Nico Huber nico.huber@secunet.com --- M ich_descriptors.h M ichspi.c 2 files changed, 57 insertions(+), 82 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/36/18936/1
diff --git a/ich_descriptors.h b/ich_descriptors.h index dbf73e2..df4dd76 100644 --- a/ich_descriptors.h +++ b/ich_descriptors.h @@ -34,7 +34,7 @@ #define ICH_RET_OOB -4
#define ICH9_REG_FDOC 0xB0 /* 32 Bits Flash Descriptor Observability Control */ -#define PCH100_REG_FDOC 0xB4 /* 32 bits FDOC in PCH */ +#define PCH100_REG_FDOC 0xB4 /* New offset from Sunrise Point on */ /* 0-1: reserved */ #define FDOC_FDSI_OFF 2 /* 2-11: Flash Descriptor Section Index */ #define FDOC_FDSI (0x3f << FDOC_FDSI_OFF) @@ -43,7 +43,7 @@ /* 15-31: reserved */
#define ICH9_REG_FDOD 0xB4 /* 32 Bits Flash Descriptor Observability Data */ -#define PCH100_REG_FDOD 0xB8 /* 32 bits FDOD in PCH */ +#define PCH100_REG_FDOD 0xB8 /* New offset from Sunrise Point on */
/* Field locations and semantics for LVSCC, UVSCC and related words in the flash * descriptor are equal therefore they all share the same macros below. */ diff --git a/ichspi.c b/ichspi.c index ac859e0..81da495 100644 --- a/ichspi.c +++ b/ichspi.c @@ -33,6 +33,25 @@ #include "spi.h" #include "ich_descriptors.h"
+/* Sunrise Point */ + +/* Added HSFS Status bits */ +#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */ +#define HSFS_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) +#define HSFS_PRR34LCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ +#define HSFS_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) +/* HSFS_BERASE vanished */ + +/* Changed HSFC Control bits */ +#define PCH100_HSFC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ +#define PCH100_HSFC_FCYCLE (0x7 << PCH100_HSFC_FCYCLE_OFF) + +#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ + +#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ +#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ +#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */ + /* ICH9 controller register definition */ #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ #define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ @@ -169,50 +188,6 @@ #define ICH7_REG_PREOP 0x54 /* 16 Bits */ #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ - -/*SUNRISE point*/ -/* 32 Bits Hardware Sequencing Flash Status */ -#define PCH100_REG_HSFSC 0x04 -/*Status bits*/ -#define HSFSC_FDONE_OFF 0 /* 0: Flash Cycle Done */ -#define HSFSC_FDONE (0x1 << HSFSC_FDONE_OFF) -#define HSFSC_FCERR_OFF 1 /* 1: Flash Cycle Error */ -#define HSFSC_FCERR (0x1 << HSFSC_FCERR_OFF) -#define HSFSC_AEL_OFF 2 /* 2: Access Error Log */ -#define HSFSC_AEL (0x1 << HSFSC_AEL_OFF) -#define HSFSC_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ -#define HSFSC_SCIP (0x1 << HSFSC_SCIP_OFF) - /* 6-10: reserved */ -/* 11: Flash Configuration Lock-Down WRSDIS */ -#define HSFSC_WRSDIS_OFF 11 -#define HSFSC_WRSDIS (0x1 << HSFSC_WRSDIS_OFF) -#define HSFSC_PRR34LCKDN_OFF 12 -#define HSFSC_PRR34LCKDN (0x1 << HSFSC_PRR34LCKDN_OFF) -/* 13: Flash Descriptor Override Pin-Strap Status */ -#define HSFSC_FDOPSS_OFF 13 -#define HSFSC_FDOPSS (0x1 << HSFSC_FDOPSS_OFF) -#define HSFSC_FDV_OFF 14 /* 14: Flash Descriptor Valid */ -#define HSFSC_FDV (0x1 << HSFSC_FDV_OFF) -#define HSFSC_FLOCKDN_OFF 15 /* 11: Flash Configuration Lock-Down */ -#define HSFSC_FLOCKDN (0x1 << HSFSC_FLOCKDN_OFF) -/*Control bits*/ -#define HSFSC_FGO_OFF 0 /* 0: Flash Cycle Go */ -#define HSFSC_FGO (0x1 << HSFSC_FGO_OFF) -#define HSFSC_FCYCLE_OFF 1 /* 1-3: FLASH Cycle */ -#define HSFSC_FCYCLE (0x3 << HSFSC_FCYCLE_OFF) -#define HSFSC_FDBC_OFF 8 /*8-13 : Flash Data Byte Count */ -#define HSFSC_FDBC (0x3f << HSFSC_FDBC_OFF) - -#define PCH100_REG_FADDR 0x08 /* 32 Bits */ -#define PCH100_REG_FDATA0 0x10 /* 64 Bytes */ - -#define PCH100_REG_FPR0 0x84 /* 32 Bytes Protected Range 0 */ -#define PCH_WP_OFF 31 /* 31: write protection enable */ -#define PCH_RP_OFF 15 /* 15: read protection enable */ - -#define PCH100_REG_PREOP_OPTYPE 0xA4 /* 32 Bits */ -#define PCH100_REG_OPMENU_LOWER 0xA8 /* 32 Bits */ -#define PCH100_REG_OPMENU_UPPER 0xAC /* 32 Bits */
/* ICH SPI configuration lock-down. May be set during chipset enabling. */ static int ichspi_lock = 0; @@ -1442,8 +1417,8 @@ /* Sets FLA in FADDR to (addr & 0x07FFFFFF) without touching other bits. */ static void pch_hwseq_set_addr(uint32_t addr) { - uint32_t addr_old = REGREAD32(PCH100_REG_FADDR) & ~0x07FFFFFF; - REGWRITE32(PCH100_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); + uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x07FFFFFF; + REGWRITE32(ICH9_REG_FADDR, (addr & 0x07FFFFFF) | addr_old); }
/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes @@ -1470,22 +1445,22 @@ uint32_t addr;
timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = REGREAD16(PCH100_REG_HSFSC)) & - (HSFSC_FDONE | HSFSC_FCERR)) == 0) && + while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & + (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { programmer_delay(8); } - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); if (!timeout) { - addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; msg_perr("Timeout error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); return 1; }
- if (hsfs & HSFSC_FCERR) { - addr = REGREAD32(PCH100_REG_FADDR) & 0x07FFFFFF; + if (hsfs & HSFS_FCERR) { + addr = REGREAD32(ICH9_REG_FADDR) & 0x07FFFFFF; msg_perr("Transaction error between offset 0x%08x and " "0x%08x (= 0x%08x + %d)!\n", addr, addr + len - 1, addr, len - 1); @@ -1556,14 +1531,14 @@ msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
- hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* clear operation */ - hsfc |= (0x3 << HSFSC_FCYCLE_OFF); /* set erase operation */ - hsfc |= HSFSC_FGO; /* start */ + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ + hsfc |= HSFC_FGO; /* start */ msg_pdbg("HSFC used for block erasing: "); - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + REGWRITE16(ICH9_REG_HSFC, hsfc);
if (pch_hwseq_wait_for_cycle_complete(timeout, len)) return -1; @@ -1587,22 +1562,22 @@ msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
- REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
while (len > 0) { block_len = min(len, flash->mst->opaque.max_data_read); pch_hwseq_set_addr(addr); - hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* set read operation */ - hsfc &= ~HSFSC_FDBC; /* clear byte count */ + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* set read operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); - hsfc |= HSFSC_FGO; /* start */ - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc);
if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) return 1; - ich_read_data(buf, block_len, PCH100_REG_FDATA0); + ich_read_data(buf, block_len, ICH9_REG_FDATA0); addr += block_len; buf += block_len; len -= block_len; @@ -1625,20 +1600,20 @@
msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - REGWRITE16(PCH100_REG_HSFSC, REGREAD16(PCH100_REG_HSFSC)); + REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
while (len > 0) { pch_hwseq_set_addr(addr); block_len = min(len, flash->mst->opaque.max_data_write); - ich_fill_data(buf, block_len, PCH100_REG_FDATA0); - hsfc = REGREAD16(PCH100_REG_HSFSC + 2); - hsfc &= ~HSFSC_FCYCLE; /* clear operation */ - hsfc |= (0x2 << HSFSC_FCYCLE_OFF); /* set write operation */ - hsfc &= ~HSFSC_FDBC; /* clear byte count */ + ich_fill_data(buf, block_len, ICH9_REG_FDATA0); + hsfc = REGREAD16(ICH9_REG_HSFC); + hsfc &= ~PCH100_HSFC_FCYCLE; /* clear operation */ + hsfc |= (0x2 << PCH100_HSFC_FCYCLE_OFF); /* set write operation */ + hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFSC_FDBC_OFF) & HSFSC_FDBC); - hsfc |= HSFSC_FGO; /* start */ - REGWRITE16(PCH100_REG_HSFSC + 2, hsfc); + hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + REGWRITE16(ICH9_REG_HSFC, hsfc);
if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) return -1; @@ -1937,17 +1912,17 @@ return ERROR_FATAL; } free(arg); - tmp = mmio_readl(ich_spibar + PCH100_REG_HSFSC); + tmp = mmio_readl(ich_spibar + ICH9_REG_HSFS); msg_pdbg("0x04: 0x%04x (HSFSC)\n", tmp); - if (tmp & HSFSC_FLOCKDN) { + if (tmp & HSFS_FLOCKDN) { msg_perr("WARNING: SPI Configuration " "Lockdown activated.\n"); ichspi_lock = 1; } - if (tmp & HSFSC_FDV) + if (tmp & HSFS_FDV) desc_valid = 1;
- if (!(tmp & HSFSC_FDOPSS) && desc_valid) + if (!(tmp & HSFS_FDOPSS) && desc_valid) msg_perr("The Flash Descriptor Security Override " "Strap-Pin is set. Restrictions implied\n" "by the FRAP and FREG registers are NOT in " @@ -1955,7 +1930,7 @@ "Range (PR) restrictions still apply.\n"); ich_init_opcodes();
- tmp = mmio_readl(ich_spibar + PCH100_REG_FADDR); + tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp); if (desc_valid) { tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
-
Nico Huber (Code Review)