Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/62282 )
Change subject: ichspi: Add Jasper Lake support ......................................................................
ichspi: Add Jasper Lake support
Change-Id: Ib942d0b8942fe0a991b2af0b187414818485153d Signed-off-by: Edward O'Callaghan quasisec@google.com --- M chipset_enable.c M ich_descriptors.c M ichspi.c M programmer.h M util/ich_descriptors_tool/ich_descriptors_tool.c 5 files changed, 27 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/82/62282/1
diff --git a/chipset_enable.c b/chipset_enable.c index d9a1d3a..b68e531 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1009,6 +1009,11 @@ return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE); }
+static int enable_flash_jlk(struct pci_dev *const dev, const char *const name) +{ + return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_JASPER_LAKE); +} + /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. * @@ -2113,6 +2118,7 @@ {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl}, {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk}, {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk}, + {0x8086, 0x4da4, B_S, DEP, "Intel", "Jasper Lake", enable_flash_jlk}, {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc}, {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300}, {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300}, diff --git a/ich_descriptors.c b/ich_descriptors.c index 0ce5720..499ec0e 100644 --- a/ich_descriptors.c +++ b/ich_descriptors.c @@ -41,6 +41,7 @@ switch (cs) { case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: return 6; case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_300_SERIES_CANNON_POINT: @@ -73,6 +74,7 @@ case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (cont->NM <= MAX_NUM_MASTERS) return cont->NM; @@ -111,7 +113,7 @@ "8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg", "9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point", "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point", - "500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Elkhart Lake", + "500 series Tiger Point", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake", }; if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names)) cs = 0; @@ -208,6 +210,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: { uint8_t size_enc; if (idx == 0) { @@ -298,6 +301,7 @@ return freq_str[1][value]; case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: return freq_str[2][value]; case CHIPSET_500_SERIES_TIGER_POINT: return freq_str[3][value]; @@ -348,6 +352,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: has_flill1 = true; break; @@ -528,7 +533,8 @@ desc->master.mstr[i].write & (1 << j) ? 'w' : ' '); msg_pdbg2("\n"); } - } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_ELKHART_LAKE) { + } else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE || cs == CHIPSET_JASPER_LAKE + || cs == CHIPSET_ELKHART_LAKE) { const char *const master_names[] = { "BIOS", "TXE", }; if (nm > (ssize_t)ARRAY_SIZE(master_names)) { msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM); @@ -1055,6 +1061,7 @@ case CHIPSET_400_SERIES_COMET_POINT: case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: /* `freq_read` was repurposed, so can't check on it any more. */ break; @@ -1212,6 +1219,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: if (idx == 0) { size_enc = desc->component.dens_new.comp1_density; @@ -1251,6 +1259,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: mmio_le_writel(control, spibar + PCH100_REG_FDOC); return mmio_le_readl(spibar + PCH100_REG_FDOD); diff --git a/ichspi.c b/ichspi.c index 117ff8d..5889f3a 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1783,6 +1783,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_pr = 6; /* Includes GPR0 */ *reg_pr0 = PCH100_REG_FPR0; @@ -1819,6 +1820,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: *num_freg = 16; break; @@ -1877,6 +1879,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: tmp = mmio_readl(spibar + PCH100_REG_DLOCK); msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); @@ -1954,6 +1957,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_BAYTRAIL: case CHIPSET_ELKHART_LAKE: break; @@ -1990,6 +1994,7 @@ case CHIPSET_500_SERIES_TIGER_POINT: case CHIPSET_APOLLO_LAKE: case CHIPSET_GEMINI_LAKE: + case CHIPSET_JASPER_LAKE: case CHIPSET_ELKHART_LAKE: break; default: @@ -2030,6 +2035,7 @@ if (ich_spi_mode == ich_auto && (ich_gen == CHIPSET_APOLLO_LAKE || ich_gen == CHIPSET_GEMINI_LAKE || + ich_gen == CHIPSET_JASPER_LAKE || ich_gen == CHIPSET_ELKHART_LAKE)) { msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n"); ich_spi_mode = ich_hwseq; diff --git a/programmer.h b/programmer.h index 08e5e9c..003d7af 100644 --- a/programmer.h +++ b/programmer.h @@ -352,6 +352,7 @@ CHIPSET_500_SERIES_TIGER_POINT, CHIPSET_APOLLO_LAKE, CHIPSET_GEMINI_LAKE, + CHIPSET_JASPER_LAKE, CHIPSET_ELKHART_LAKE, };
diff --git a/util/ich_descriptors_tool/ich_descriptors_tool.c b/util/ich_descriptors_tool/ich_descriptors_tool.c index f743510..303ca7f 100644 --- a/util/ich_descriptors_tool/ich_descriptors_tool.c +++ b/util/ich_descriptors_tool/ich_descriptors_tool.c @@ -128,6 +128,7 @@ "\t- "silvermont" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n" "\t- "apollo" for Intel's Apollo Lake SoC.\n" "\t- "gemini" for Intel's Gemini Lake SoC.\n" +"\t- "jasper" for Intel's Jasper Lake SoC.\n" "\t- "5" or "ibex" for Intel's 5 series chipsets,\n" "\t- "6" or "cougar" for Intel's 6 series chipsets,\n" "\t- "7" or "panther" for Intel's 7 series chipsets.\n" @@ -238,6 +239,8 @@ cs = CHIPSET_APOLLO_LAKE; else if (strcmp(csn, "gemini") == 0) cs = CHIPSET_GEMINI_LAKE; + else if (strcmp(csn, "jasper") == 0) + cs = CHIPSET_JASPER_LAKE; else if (strcmp(csn, "elkhart") == 0) cs = CHIPSET_ELKHART_LAKE; }
-
Edward O'Callaghan (Code Review)