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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
I would expect the hardware to coordinate between the different masters.
I guess a simple experiment could give a hint if it does: The hardware is also
able to start cycles on its own for memory-mapped flash access. You could test
if this toggles the SCIP bit in the host master interface. For instance, poll
SCIP and then read from the memory-mapped BIOS area. If polling too fast is an
issue, I'd measure the time of a short cycle, then take half of that as the polling
delay.
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