Change in flashrom[master]: ichspi: Define `Write Enable Type (WET)` register under HSFC

[Subrata Banik (Code Review)]

Attention is currently required from: Subrata Banik, Nico Huber, Angel Pons.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/62888 )

Change subject: ichspi: Define `Write Enable Type (WET)` register under HSFC
......................................................................

Patch Set 6:

(1 comment)

File ichspi.c:

https://review.coreboot.org/c/flashrom/+/62888/comment/f3c47ecc_1c6986a3 
PS6, Line 91: /* New HSFC Control bit */
> > > If you have doubts that the bit was introduced with PCH100, you can always
> > > test the hardware.
> >
> > Do we have any action item here regarding the open comment or we are good here ?
>
> If you think the code should be changed because the bit existed earlier,
> you should confirm that by testing the bit on respective hardware. If it
> didn't exist earlier, there is nothing to change, I suppose.

If we have this bit defined for PCH100 onwards then should renamed it with `PCH100_` prefix, else we can drop these macros as remain unused.
> > Ref to Intel doc 355845 section 22.1.3. Bit 7:3 are reserved, so, WET bit does exist there.
>
> I can't find that document, what is its title? And I don't understand,

Doc title:
Intel® I/O Controller Hub 9 (ICH9)
Family
External Design Specification (EDS)
– For the Intel® 82801IB ICH9, 82801IR ICH9R, and 82801IH ICH9DH,
82801IO ICH9DO, 82801IBM ICH9M, 82801IEM ICH9M-E,
and ICH9M-SFF I/O Controller Hubs
> why does it exist when the doc says reserved?

that is my question too. 😊