[M] Change in flashrom[main]: flashchips: Add XMC25QH6A

[Eric Park (Code Review)]

Eric Park has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/86990?usp=email )

Change subject: flashchips: Add XMC25QH6A
......................................................................

flashchips: Add XMC25QH6A

Based off of the now-abandoned GitHub pull request here:
https://github.com/flashrom/flashrom/pull/239

This commit applies the changes on top of the refactor where the flash
chip declarations were separated by vendor.

Change-Id: I5b11e30f0a5357a6cbb32ddb93f450de5364c60b
Co-authored-by: Ayushman Dutta 
Co-authored-by: "aiyion.prime" 
Signed-off-by: Eric Park 
---
M flashchips/xmc.c
M include/flashchips.h
2 files changed, 58 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/90/86990/1

diff --git a/flashchips/xmc.c b/flashchips/xmc.c
index 4ed0225..ac384a9 100644
--- a/flashchips/xmc.c
+++ b/flashchips/xmc.c
@@ -248,6 +248,47 @@

{
    	.vendor		= "XMC",
+		.name		= "XM25QH64A",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= XMC_ID,
+		.model_id	= XMC_XM25QH64A,
+		.total_size	= 8192,
+		.page_size	= 256,
+		/* supports SFDP */
+		/* OTP: 512B total; enter 0x3A */
+		/* QPI enable 0x38, disable 0xFF */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+		.tested		= TEST_OK_PREW,
+		.probe		= probe_spi_rdid,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 2048} },
+				.block_erase = spi_block_erase_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 256} },
+				.block_erase = spi_block_erase_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 128} },
+				.block_erase = spi_block_erase_d8,
+			}, {
+				.eraseblocks = { { 8192 * 1024, 1} },
+				.block_erase = spi_block_erase_60,
+			}, {
+				.eraseblocks = { { 8192 * 1024, 1} },
+				.block_erase = spi_block_erase_c7,
+			}
+		},
+		.printlock	= spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */
+		.unlock		= spi_disable_blockprotect_bp3_srwd,
+		.write		= spi_chip_write_256,
+		.read		= spi_chip_read,
+		.voltage	= {2700, 3600},
+	},
+
+	{
+		.vendor		= "XMC",
    	.name		= "XM25QH64C/XM25QH64D",
    	.bustype	= BUS_SPI,
    	.manufacture_id	= ST_ID,
diff --git a/include/flashchips.h b/include/flashchips.h
index 556729c..f59b7ce 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -1082,6 +1082,23 @@
 #define WINBOND_W49V002A	0xB0
 #define WINBOND_W49V002FA	0x32

+#define XMC_ID          0x20    /* same as ST_ID */
+#define XMC_XM25QH256B  0x6019
+#define XMC_XM25QH128A  0x1708
+#define XMC_XM25QH128B  0x6018
+#define XMC_XM25QH64A   0x7017
+#define XMC_XM25QH64B   0x6017
+#define XMC_XM25QH32B   0x4016  /* 0x6016 for QPI mode */
+#define XMC_XM25QH16B   0x4015
+#define XMC_XM25QH80B   0x4014
+#define XMC_XM25QH40B   0x4013
+#define XMC_XM25QU256B  0x7019
+#define XMC_XM25QU128B  0x5018
+#define XMC_XM25QU64A   0x3817
+#define XMC_XM25QU64B   0x5017
+#define XMC_XM25QU40B   0x5013
+#define XMC_XM25QU20B   0x5012
+
 #define XTX_ID			0x0B	/* XTX Technology Limited */
 #define XTX_XT25F02E		0x4012
 #define XTX_XT25F64B		0x4017