[S] Change in flashrom[main]: flashchips: Add support for MXIC MX25L3273F

[DZ (Code Review)]

DZ has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/81562?usp=email )

Change subject: flashchips: Add support for MXIC MX25L3273F
......................................................................

flashchips: Add support for MXIC MX25L3273F

The MX25L12850F has been tested by ch341a programmer : read, write,
erase and wp.

We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.

MX25L12850F datasheet is available at the following URL:
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8661/MX25L3273F,%203V,%2...

Change-Id: I4adaaa796d1db34702e7b0ed8e6fb167a3a5f6d7
Signed-off-by: DanielZhang 
---
M flashchips.c
1 file changed, 46 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/81562/1

diff --git a/flashchips.c b/flashchips.c
index 204f34f..7833031 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -9465,6 +9465,52 @@
    	},
    	.decode_range	= DECODE_RANGE_SPI25_BIT_CMP,
    },
+        {
+		.vendor		= "Macronix",
+		.name		= "MX25L3273F",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= MACRONIX_ID,
+		.model_id	= MACRONIX_MX25L3205,
+		.total_size	= 4096,
+		.page_size	= 256,
+		/* OTP: 1024B total; enter 0xB1, exit 0xC1 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR,
+		.tested		= TEST_OK_PREWB,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 128} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 64} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {4 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {4 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit 6 is quad enable */
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {2650, 3600},
+		.reg_bits	=
+		{
+			.srp    = {STATUS1, 7, RW},
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW},  {STATUS1, 5, RW}},
+			.tb     = {CONFIG, 3, OTP}
+		},
+
+		.decode_range	= DECODE_RANGE_SPI25,
+        },

{
    	.vendor		= "Macronix",