Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
to look at the new patch set (#3).
Change subject: ichspi: Add support for Intel Skylake
ichspi: Add support for Intel Skylake
The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:
* Support for more flash regions moved PR* registers
* Only 4KiB erase blocks are supported by the primary erase command
* A second erase command for 64KiB pages was added
* More commands were added for status register access etc.
* A "Dedicated Lock Bits" register was added
No support for the new commands was added.
The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.
Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:
Author: Ramya Vijaykumar <ramya.vijaykumar(a)intel.com>
flashrom: Add Skylake platform support
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
3 files changed, 228 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/3
To view, visit https://review.coreboot.org/18962
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <dhendrix(a)chromium.org>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at>
Gerrit-Reviewer: build bot (Jenkins)