[M] Change in flashrom[master]: ichspi: Factor out common hwseq_xfer logic into helpers

[Subrata Banik (Code Review)]

Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons.

Hello build bot (Jenkins), Nico Huber, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/62869

to look at the new patch set (#27).

Change subject: ichspi: Factor out common hwseq_xfer logic into helpers
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ichspi: Factor out common hwseq_xfer logic into helpers

List of changes:
1. Add a unified `execute SPI flash transfer` function that does:
   - Check the SCIP bit prior initiate new operation.
   - Start the transfer by setting address and length for transfer,
     finally set FGO bit.
   - Wait for the transaction to get completed/failed/timed out.
2. All HW Sequencing SPI operation uses `execute SPI flash transfer`
   function

Note:
The refactoring xfer logic here assumes setting `HSFC_FDBC to 0` while
performing erase operation using `ich_hwseq_block_erase()`. But it does
not impact the erase operations.

BUG=b:223630977
TEST=Able to perform read-status/write-status/read/write/erase
operation on PCH 600 series chipset (board name: google/kano).

Signed-off-by: Subrata Banik 
Change-Id: Ic9fd50841449e02f476a8834f4642d6ecad36dc3
---
M ichspi.c
1 file changed, 82 insertions(+), 90 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/62869/27