[S] Change in flashrom[1.0.x]: chipset_enable.c: check return value from rphysmap() call

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67842 )

Change subject: chipset_enable.c: check return value from rphysmap() call
......................................................................

chipset_enable.c: check return value from rphysmap() call

Port from the ChromiumOS fork of flashrom.

Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476
Signed-off-by: Edward O'Callaghan 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444
Tested-by: build bot (Jenkins) 
Reviewed-by: Sam McNally 
Reviewed-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67842
Reviewed-by: Felix Singer 
Reviewed-by: Edward O'Callaghan 
---
M chipset_enable.c
1 file changed, 21 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Singer: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Edward O'Callaghan: Looks good to me, approved

diff --git a/chipset_enable.c b/chipset_enable.c
index 3437792..67ce761 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -934,6 +934,8 @@
    uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
    msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
    void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
+	if (spibar == ERROR_PTR)
+		return ERROR_FATAL;

/* Enable Flash Writes.
     * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).