Change in flashrom[master]: ichspi: Extract initialisation of swseq and hwseq into a function

[Anastasia Klimchuk (Code Review)]

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/58737 )

Change subject: ichspi: Extract initialisation of swseq and hwseq into a function
......................................................................

ichspi: Extract initialisation of swseq and hwseq into a function

Initialisation of swseq_data and hwseq_data gets its own function,
which is called from init_ich_default. This makes init_ich_default
more readable.

This patch also gives a name to (previously anonymous) struct
swseq_data. Its sibling struct hwseq_data already has a name. Structs
need names to be able to daclare function parameters.

TEST ME ON HW

BUG=b:204488958

Change-Id: I7d62b1b380e497b82dcae1284d752204cc541bd3
Signed-off-by: Anastasia Klimchuk 
---
M ichspi.c
1 file changed, 54 insertions(+), 48 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/37/58737/1

diff --git a/ichspi.c b/ichspi.c
index 7a9c5cd..0966ec6 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -504,7 +504,7 @@
    pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
 }

-static struct {
+static struct swseq_data {
    size_t reg_ssfsc;
    size_t reg_preop;
    size_t reg_optype;
@@ -1782,6 +1782,58 @@
    return 0;
 }

+static void init_swseq_hwseq(struct swseq_data *swseq, struct hwseq_data *hwseq,
+			    size_t *num_freg, size_t *num_pr, size_t *reg_pr0,
+			    enum ich_chipset ich_gen)
+{
+	/* Moving registers / bits */
+	switch (ich_gen) {
+	case CHIPSET_100_SERIES_SUNRISE_POINT:
+	case CHIPSET_C620_SERIES_LEWISBURG:
+	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_400_SERIES_COMET_POINT:
+	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
+		*num_pr			= 6;	/* Includes GPR0 */
+		*reg_pr0		= PCH100_REG_FPR0;
+		swseq->reg_ssfsc	= PCH100_REG_SSFSC;
+		swseq->reg_preop	= PCH100_REG_PREOP;
+		swseq->reg_optype	= PCH100_REG_OPTYPE;
+		swseq->reg_opmenu	= PCH100_REG_OPMENU;
+		hwseq->addr_mask	= PCH100_FADDR_FLA;
+		hwseq->only_4k		= true;
+		hwseq->hsfc_fcycle	= PCH100_HSFC_FCYCLE;
+		break;
+	default:
+		*num_pr			= 5;
+		*reg_pr0		= ICH9_REG_PR0;
+		swseq->reg_ssfsc	= ICH9_REG_SSFS;
+		swseq->reg_preop	= ICH9_REG_PREOP;
+		swseq->reg_optype	= ICH9_REG_OPTYPE;
+		swseq->reg_opmenu	= ICH9_REG_OPMENU;
+		hwseq->addr_mask	= ICH9_FADDR_FLA;
+		hwseq->only_4k		= false;
+		hwseq->hsfc_fcycle	= HSFC_FCYCLE;
+		break;
+	}
+	switch (ich_gen) {
+	case CHIPSET_100_SERIES_SUNRISE_POINT:
+		*num_freg = 10;
+		break;
+	case CHIPSET_C620_SERIES_LEWISBURG:
+		*num_freg = 12;	/* 12 MMIO regs, but 16 regions in FD spec */
+		break;
+	case CHIPSET_300_SERIES_CANNON_POINT:
+	case CHIPSET_400_SERIES_COMET_POINT:
+	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
+		*num_freg = 16;
+		break;
+	default:
+		*num_freg = 5;
+		break;
+	}
+}

static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
 {
@@ -1798,53 +1850,7 @@
    ich_generation = ich_gen;
    ich_spibar = spibar;

-	/* Moving registers / bits */
-	switch (ich_gen) {
-	case CHIPSET_100_SERIES_SUNRISE_POINT:
-	case CHIPSET_C620_SERIES_LEWISBURG:
-	case CHIPSET_300_SERIES_CANNON_POINT:
-	case CHIPSET_400_SERIES_COMET_POINT:
-	case CHIPSET_APOLLO_LAKE:
-	case CHIPSET_GEMINI_LAKE:
-		num_pr			= 6;	/* Includes GPR0 */
-		reg_pr0			= PCH100_REG_FPR0;
-		swseq_data.reg_ssfsc	= PCH100_REG_SSFSC;
-		swseq_data.reg_preop	= PCH100_REG_PREOP;
-		swseq_data.reg_optype	= PCH100_REG_OPTYPE;
-		swseq_data.reg_opmenu	= PCH100_REG_OPMENU;
-		hwseq_data.addr_mask	= PCH100_FADDR_FLA;
-		hwseq_data.only_4k	= true;
-		hwseq_data.hsfc_fcycle	= PCH100_HSFC_FCYCLE;
-		break;
-	default:
-		num_pr			= 5;
-		reg_pr0			= ICH9_REG_PR0;
-		swseq_data.reg_ssfsc	= ICH9_REG_SSFS;
-		swseq_data.reg_preop	= ICH9_REG_PREOP;
-		swseq_data.reg_optype	= ICH9_REG_OPTYPE;
-		swseq_data.reg_opmenu	= ICH9_REG_OPMENU;
-		hwseq_data.addr_mask	= ICH9_FADDR_FLA;
-		hwseq_data.only_4k	= false;
-		hwseq_data.hsfc_fcycle	= HSFC_FCYCLE;
-		break;
-	}
-	switch (ich_gen) {
-	case CHIPSET_100_SERIES_SUNRISE_POINT:
-		num_freg = 10;
-		break;
-	case CHIPSET_C620_SERIES_LEWISBURG:
-		num_freg = 12;	/* 12 MMIO regs, but 16 regions in FD spec */
-		break;
-	case CHIPSET_300_SERIES_CANNON_POINT:
-	case CHIPSET_400_SERIES_COMET_POINT:
-	case CHIPSET_APOLLO_LAKE:
-	case CHIPSET_GEMINI_LAKE:
-		num_freg = 16;
-		break;
-	default:
-		num_freg = 5;
-		break;
-	}
+	init_swseq_hwseq(&swseq_data, &hwseq_data, &num_freg, &num_pr, &reg_pr0, ich_gen);

int ret = get_ich_spi_mode_param(&ich_spi_mode);
    if (ret)