Change in flashrom[staging]: fixup! flashrom: Add Skylake platform support

[Nico Huber (Code Review)]

Nico Huber has uploaded a new change for review. ( https://review.coreboot.org/18940 )

Change subject: fixup! flashrom: Add Skylake platform support
......................................................................

fixup! flashrom: Add Skylake platform support

ichspi: Decode DLOCK register

Change-Id: Idc57fec7c2007926dafd8b84119d15e86c5e111d
Signed-off-by: Nico Huber 
---
M ichspi.c
1 file changed, 43 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/18940/1

diff --git a/ichspi.c b/ichspi.c
index 413d97c..3ff0c55 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -48,6 +48,28 @@

#define PCH100_FADDR_FLA	0x07ffffff

+#define PCH100_REG_DLOCK	0x0c	/* 32 Bits Discrete Lock Bits */
+#define DLOCK_BMWAG_LOCKDN_OFF	0
+#define DLOCK_BMWAG_LOCKDN	(0x1 << DLOCK_BMWAG_LOCKDN_OFF)
+#define DLOCK_BMRAG_LOCKDN_OFF	1
+#define DLOCK_BMRAG_LOCKDN	(0x1 << DLOCK_BMRAG_LOCKDN_OFF)
+#define DLOCK_SBMWAG_LOCKDN_OFF	2
+#define DLOCK_SBMWAG_LOCKDN	(0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
+#define DLOCK_SBMRAG_LOCKDN_OFF	3
+#define DLOCK_SBMRAG_LOCKDN	(0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
+#define DLOCK_PR0_LOCKDN_OFF	8
+#define DLOCK_PR0_LOCKDN	(0x1 << DLOCK_PR0_LOCKDN_OFF)
+#define DLOCK_PR1_LOCKDN_OFF	9
+#define DLOCK_PR1_LOCKDN	(0x1 << DLOCK_PR1_LOCKDN_OFF)
+#define DLOCK_PR2_LOCKDN_OFF	10
+#define DLOCK_PR2_LOCKDN	(0x1 << DLOCK_PR2_LOCKDN_OFF)
+#define DLOCK_PR3_LOCKDN_OFF	11
+#define DLOCK_PR3_LOCKDN	(0x1 << DLOCK_PR3_LOCKDN_OFF)
+#define DLOCK_PR4_LOCKDN_OFF	12
+#define DLOCK_PR4_LOCKDN	(0x1 << DLOCK_PR4_LOCKDN_OFF)
+#define DLOCK_SSEQ_LOCKDN_OFF	16
+#define DLOCK_SSEQ_LOCKDN	(0x1 << DLOCK_SSEQ_LOCKDN_OFF)
+
 #define PCH100_REG_FPR0		0x84	/* 32 Bytes Protected Range 0 */

#define PCH100_REG_SSFSC	0xA0	/* 32 Bits Status (8) + Control (24) */
@@ -391,6 +413,21 @@
    pprint_reg(SSFC, DBC, reg_val, ", ");
    pprint_reg(SSFC, SME, reg_val, ", ");
    pprint_reg(SSFC, SCF, reg_val, "\n");
+}
+
+static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
+{
+	msg_pdbg("DLOCK: ");
+	pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ", ");
+	pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
 }

static struct {
@@ -1751,6 +1788,12 @@
    	tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
    	msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);

+		if (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
+			const uint32_t dlock = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
+			msg_pdbg("0x0c: 0x%08x (DLOCK)\n", dlock);
+			prettyprint_pch100_reg_dlock(dlock);
+		}
+
    	if (desc_valid) {
    		tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
    		msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);