Change in flashrom[staging]: ichspi: Add support for Intel Skylake

[Nico Huber (Code Review)]

Hello Stefan Tauner, Youness Alaoui, David Hendricks, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/18962

to look at the new patch set (#7).

Change subject: ichspi: Add support for Intel Skylake
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ichspi: Add support for Intel Skylake

The Sunrise Point PCH, paired with Skylake, has some minor changes
in the HW sequencing interface:

* Support for more flash regions moved PR* registers
  * Only 4KiB erase blocks are supported by the primary erase command
  * A second erase command for 64KiB pages was added
  * More commands were added for status register access etc.
  * A "Dedicated Lock Bits" register was added

No support for the new commands was added.

The SW sequencing interface seems to have moved register location and
is not supported any more officially. It's also untested.

Changes are loosely based on the Skylake support commit in Chromium OS
by Ramya Vijaykumar:

commit a9a64f9e4d52c39fcd3c5f7d7b88065baed189b1
  Author: Ramya Vijaykumar

flashrom: Add Skylake platform support

Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Signed-off-by: Nico Huber 
---
M ich_descriptors.c
M ich_descriptors.h
M ichspi.c
3 files changed, 227 insertions(+), 87 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/62/18962/7