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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/61854 )
Change subject: ichspi.c: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
@Nico, i didn't understand the comment about "cover up the actual problem", the code change in question is not a work around, but a recommendation in the chipset EDS.
The problem description was that multiple processes might use the registers at
once. And as was explained before, the SCIP bit is not meant to be used to
synchronize between multiple processes, and doesn't suffice to do so. Hence,
trying to synchronize via SCIP covers up that there are more severe problems
when using the register interface from mutliple processes at once.
It can, in theory, also cover up problems within flashrom itself, e.g. when
the current checks _after_ the flash cycle are not sufficient.
I fully agree to the EDS recommendation. We should check the bit and if it's
set unexpectedly, bail out. If flashrom itself is responsible for the unexpectedly
set bit, fix that as well.
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