[flashrom-gerrit] Change in flashrom[master]: chipset_enable: Add support for discrete Cannon Lake PCHs

[Nico Huber (Code Review)]

Hello Thomas Heijligen, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/flashrom/+/34071

to look at the new patch set (#2).

Change subject: chipset_enable: Add support for discrete Cannon Lake PCHs
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chipset_enable: Add support for discrete Cannon Lake PCHs

The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the
Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted.

[1] Intel(R) 300 Series and Intel(R) C240 Series
    Chipset Family Platform Controller Hub
    Datasheet - Volume 1 of 2
    Revison 4 (Dec 2018)
    Document Number 337347

[2] Intel(R) 300 Series Chipset Families Platform Controller Hub
    Datasheet - Volume 2 of 2
    Revision 2? (Oct 2018)
    Document Number 337348

Change-Id: If0b54799d5b93169ee660409bad57ae14677340c
Signed-off-by: Thomas Heijligen 
Signed-off-by: Nico Huber 
---
M chipset_enable.c
M programmer.h
2 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/34071/2