Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/46089 )
Change subject: realtek_mst_i2c_spi.c: Update wp disable function ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/flashrom/+/46089/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/flashrom/+/46089/4//COMMIT_MSG@9 PS4, Line 9: The write protection trigger has been updated by the vendor so update : here as well. Please add a little more detail for external reviewers so that everyone understands the code well and folks can look back in git history to understand it as well.
Also please add BUG/BRANCH=puff and TEST lines.
https://review.coreboot.org/c/flashrom/+/46089/4/realtek_mst_i2c_spi.c File realtek_mst_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/46089/4/realtek_mst_i2c_spi.c@49 PS4, Line 49: HIGH perhaps, 'HIGHBYTE' also leave out the `_WP_` part.
Alternatively, just write `#define GPIO_CONFIG_ADDRESS 0x104F` and use `(GPIO_CONFIG_ADDRESS>>8)` to get the high byte and the cast will auto give you the low byte.