Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39687 )
Change subject: lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6} ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/flashrom/+/39687/4/lspcon_i2c_spi.c File lspcon_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/39687/4/lspcon_i2c_spi.c@333 PS4, Line 333: uint8_t command_byte1[] = { ROMADDR_BYTE1, (offset >> 8) & 0xff };
Yes this can be done in a single write, I just want to separate them to make this clear. […]
Ack
https://review.coreboot.org/c/flashrom/+/39687/4/lspcon_i2c_spi.c@406 PS4, Line 406: 256
Actually no, I have go through the code and looks like that applied to the send_command method event […]
Sounds reasonable.
https://review.coreboot.org/c/flashrom/+/39687/5/lspcon_i2c_spi.c File lspcon_i2c_spi.c:
https://review.coreboot.org/c/flashrom/+/39687/5/lspcon_i2c_spi.c@31 PS5, Line 31: #define READ_SIZE 32 Remove.