Attention is currently required from: Nico Huber, Edward O'Callaghan, Angel Pons. Xiang W has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/49255 )
Change subject: bitbang-spi.c: support clock polarity and phase ......................................................................
Patch Set 27:
(5 comments)
File bitbang_spi.c:
https://review.coreboot.org/c/flashrom/+/49255/comment/a66c18ba_b05abecb PS26, Line 34: data transmission
Technically, it's the data sampling (or capturing, as Wikipedia puts it) […]
Done
https://review.coreboot.org/c/flashrom/+/49255/comment/88c2f26b_d1c3f969 PS26, Line 96: bitbang_spi_set_sck(master, !cpol);
The first clock change always needs to happen with a delay after […]
There is no need to operate CS when sending each byte, the operation of CS is in bitbang_spi_send_command
https://review.coreboot.org/c/flashrom/+/49255/comment/ecce7cf0_1f0f1bb9 PS26, Line 121: programmer_delay(master->half_period); : bitbang_spi_set_sck_set_mosi(master, !cpol, (val >> i) & 1); : programmer_delay(master->half_period); : bitbang_spi_set_sck(master, cpol);
This does not look right and is probably what led to the follow up commit. […]
The hardware logic only requires that the data state is stable after the clock changes. The following sequence is correct： - delay - set mosi - first edge - delay - second edge
So I submitted a patch to fix bitbang_spi_set_sck_set_mosi：https://review.coreboot.org/c/flashrom/+/49264/13/bitbang_spi.c#b68
https://review.coreboot.org/c/flashrom/+/49255/comment/210f26a2_24685a38 PS26, Line 184: if (strlen(mode)) {
So an empty string is not reported as error?
Done
https://review.coreboot.org/c/flashrom/+/49255/comment/474d8d1a_b766bb26 PS26, Line 187: mode == endptr
This does not account for trailing garbage. It's better to check for […]
Done