Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/30995 )
Change subject: ichspi: Add Apollo Lake support ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/30995/1/ich_descriptors.c File ich_descriptors.c:
https://review.coreboot.org/#/c/30995/1/ich_descriptors.c@244 PS1, Line 244: 7
This should be correct. But please check this value again. My documentation says something else. […]
Ah, it's 17MHz for the read speed, 14MHz for others. It's just an informational string, should we make it "14 MHz / 17 MHz"?
https://review.coreboot.org/#/c/30995/1/ich_descriptors.c@348 PS1, Line 348: ME
On APL this is not the place for the ME/TXE image. […]
I don't think it makes it too confusing? We could make a distinction by chipset, but is it worth the effort?
Naming it "ME/TXE" maybe? I'd say it should suffice to know that it is ME/TXE related.
https://review.coreboot.org/#/c/30995/1/ich_descriptors.c@452 PS1, Line 452: TXE
This is only the TXE ROM Bypass for pre production not the whole TXE
That's right, though, does it matter that much here?
https://review.coreboot.org/#/c/30995/1/ichspi.c File ichspi.c:
https://review.coreboot.org/#/c/30995/1/ichspi.c@1758 PS1, Line 1758: num_freg = 16
Is this BIOS_FREGx from APL Datasheet 3 (334819-001)? There are only BIOS_FREG0 ... […]
You might have to scroll down, there is another set at 0xe0.