[flashrom-gerrit] Change in flashrom[master]: chipset_enable.c: Add MCP61 pid=0x03e2 support

[Stefan Reinauer (Code Review)]

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47089 )

Change subject: chipset_enable.c: Add MCP61 pid=0x03e2 support
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/flashrom/+/47089/1//COMMIT_MSG@8 
PS1, Line 8:
> Where does the ID come from?

According to https://envytools.readthedocs.io/en/latest/hw/pciid.html this is the memory controller PCI ID, not the LPC PCI ID like for all other devices in this list. Is this done on purpose?