Attention is currently required from: Michał Żygowski, Paul Menzel.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55578 )
Change subject: Add Tiger Lake U Premium support
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Patch Set 12: Code-Review+2
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/78f6f661_6d602c55
PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };
Done. […]
Thanks! that's even better :)
File flash.h:
https://review.coreboot.org/c/flashrom/+/55578/comment/76e544de_050f20ed
PS10, Line 71: BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
Hard to tell. BUS_NONSPI is mostly used on older southbridges/chipsets in chipset_enable. […]
Heh, I was wondering about that comment too. Maybe it means that once we
treat all bus types similarly in common code, we won't have to check for
SPI/NONSPI explicitly anywhere.
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