Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/44621 )
Change subject: allow 0x34 as ICCRIBA for CHIPSET_C620_SERIES_LEWISBURG ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/flashrom/+/44621/5/ich_descriptors.c File ich_descriptors.c:
https://review.coreboot.org/c/flashrom/+/44621/5/ich_descriptors.c@940 PS5, Line 940: } else if (content->ICCRIBA == 0x34) { Some feedback from Intel: Based on the PCH EDS 3.0 and the information you provided, the ICCRIBA should be the ICC initialization register ( the ICC stands for Intel Microcode technology). Due to the different SKUs of PCH parts used on DeltaLake (EVT) and (DVT), the initialization base address of the Microprocessor register is assigned by PCH to different offset address as the 4-KB boundary rules must meet, if the Program Register type. ( section 27.7.1.4.2, page 1914). It turns out that the 0x34 is the value of the Initial Base Address (offset) of the Microprocess register for A1CB QS or PRQ C621A DVT part.