13 Jul
2017
13 Jul
'17
4:04 p.m.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/18962 )
Change subject: ichspi: Add support for Intel Skylake ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/18962/7/ichspi.c File ichspi.c:
https://review.coreboot.org/#/c/18962/7/ichspi.c@49 PS7, Line 49: HSFC_WET_OFF 5
Should be bit 21?
You are off by 16 in both cases ;) the current datasheets treat HSF STS and CTL as one 32-bit register, where we treat them separately as HSFS (lower 16 bit) and HSFC (upper 16 bit).
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Gerrit-Project: flashrom
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Gerrit-Change-Id: I0f4565a3c39f5fe3aec4fc8863605cebed1ad4ee
Gerrit-Change-Number: 18962
Gerrit-PatchSet: 7
Gerrit-Owner: Nico Huber nico.h@gmx.de
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Gerrit-Reviewer: Nico Huber nico.h@gmx.de
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Gerrit-Comment-Date: Thu, 13 Jul 2017 16:04:52 +0000
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