[flashrom-gerrit] Change in flashrom[master]: flashchips: port S25FS(128S) chip from chromiumos

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/39822 )

Change subject: flashchips: port S25FS(128S) chip from chromiumos
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Patch Set 6:

(1 comment)

https://review.coreboot.org/c/flashrom/+/39822/6/spi25.c 
File spi25.c:

https://review.coreboot.org/c/flashrom/+/39822/6/spi25.c@423 
PS6, Line 423: 		if (status_reg & SPI_SR_ERA_ERR) {
> This is a block-protection bit for most chips I've seen.

Upon investigation my dyslexic eye didn't see this the first time around that this block of code comes from `s25f_poll_status():s25f.c` and is not a modification to `spi_poll_wip():spi25.c` in our tree.

Thank you for picking up on this with your sharp eye Nico!