David Hendricks has posted comments on this change. ( https://review.coreboot.org/18962 )
Change subject: ichspi: Add support for Intel Skylake ......................................................................
Patch Set 7: Code-Review-1
(2 comments)
Looks good overall. I am just a bit puzzled with a couple of offsets.
There's also a tiny merge conflict in ich_descriptors.c that is preventing rebasing.
https://review.coreboot.org/#/c/18962/7/ichspi.c File ichspi.c:
https://review.coreboot.org/#/c/18962/7/ichspi.c@46 PS7, Line 46: PCH100_HSFC_FCYCLE_OFF 1 Which datasheet did you see this in?
I think FCYCLE is bits 20:17 for 100-series and Skylake, but perhaps I'm looking in the wrong places...
https://review.coreboot.org/#/c/18962/7/ichspi.c@49 PS7, Line 49: HSFC_WET_OFF 5 Should be bit 21?