David Hendricks posted comments on this change.

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Patch set 7:Code-Review -1

Looks good overall. I am just a bit puzzled with a couple of offsets.

There's also a tiny merge conflict in ich_descriptors.c that is preventing rebasing.

(2 comments)

• File ichspi.c:

  • Patch Set #7, Line 46: PCH100_HSFC_FCYCLE_OFF 1

    Which datasheet did you see this in?

    I think FCYCLE is bits 20:17 for 100-series and Skylake, but perhaps I'm looking in the wrong places...

  • Patch Set #7, Line 49: HSFC_WET_OFF 5

    Should be bit 21?

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