Attention is currently required from: Nico Huber, Paul Menzel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/55578 )
Change subject: Add Tiger Lake U Premium support ......................................................................
Patch Set 12:
(2 comments)
File chipset_enable.c:
https://review.coreboot.org/c/flashrom/+/55578/comment/57093900_7470ae4e PS3, Line 659: { "eSPI", BUS_LPC | BUS_FWH } };
I would simply put `{ "eSPI", 0 }` here. "eSPI" is what the datasheet […]
Done. Although used BUS_NONE instead of zero
File flash.h:
https://review.coreboot.org/c/flashrom/+/55578/comment/e53feb1d_8037a854 PS10, Line 71: BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
This would definitely need an update. Although, I'm not sure if it is […]
Hard to tell. BUS_NONSPI is mostly used on older southbridges/chipsets in chipset_enable. Also there is a comment (over 5 years old) in flashrom.c:
/* * FIXME: Once all chipsets and flash chips have been updated, NONSPI * will cease to exist and should be eliminated here as well. */
which suggest there should be some cleanup.