Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/43894 )
Change subject: ichspi.c: Consolidate ich_spi_mode select into a switch stmt ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c File ichspi.c:
https://review.coreboot.org/c/flashrom/+/43894/1/ichspi.c@2011 PS1, Line 2011: "for 100+ series PCH.\n");
nit: mention Apollo Lake too?
Isn't this all done already by the strings in chipset_enable.c ? I think this is the wrong place to be printing this stuff apart from the fact that we are taking the PCH100+ path here.
snip from cros tree: ``` chipset_enable.c: {0x8086, 0x5af0, B_FS, OK, "Intel", "Apollolake", enable_flash_apl}, ```