[flashrom-gerrit] [S] Change in flashrom[main]: flashchips: Add Support for XMC XM25QH512C/XM25QH512D

[Ssunk (Code Review)]

Ssunk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83242?usp=email )

Change subject: flashchips: Add Support for XMC XM25QH512C/XM25QH512D
......................................................................

flashchips: Add Support for XMC XM25QH512C/XM25QH512D

Add initial support for the SPI flash chip XM25QH512C/XM25QH512D
Datasheet link: https://www.xmcwh.com/uploads/803/XM25QH512C_V1.6.pdf

Tested with ch341a programmer: probe, read, write, erase

Change-Id: Ica8ed5eaba2435a9416274b94f633ea40dfeea2f
Signed-off-by: Kan Sun 
---
M flashchips.c
M include/flashchips.h
2 files changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/83242/1

diff --git a/flashchips.c b/flashchips.c
index 61c2127..64677ca 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -22434,6 +22434,54 @@
    },

{
+		.vendor		= "XMC",
+		.name		= "XM25QH512C/XM25QH512D",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= ST_ID,
+		.model_id	= XMC_XM25QH512C,
+		.total_size	= 64*1024,
+		.page_size	= 256,
+		/* supports SFDP */
+		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
+		/* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN
+			| FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ,
+		.tested		= TEST_OK_PREW,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 16384} },
+				.block_erase = SPI_BLOCK_ERASE_21,
+			}, {
+			  .eraseblocks = { {4 * 1024, 16384} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 2048} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_DC,
+			}, {
+				.eraseblocks = { {64 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */
+		.unlock		= SPI_DISABLE_BLOCKPROTECT,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ,
+		.voltage	= {2700, 3600},
+	},
+
+	{
    	.vendor		= "XTX Technology Limited",
    	.name		= "XT25F02E",
    	.bustype	= BUS_SPI,
diff --git a/include/flashchips.h b/include/flashchips.h
index 9b4b2f9..e4a9e28 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -858,6 +858,7 @@
 #define XMC_XM25QH256C		0x4019	/* Same as XM25QH256D */
 #define XMC_XM25QU256C		0x4119	/* Same as XM25QU256D */
 #define XMC_XM25RU256C		0x4419
+#define XMC_XM25QH512C		0x4020	/* Same as XM25QH512D */
 #define ST_M25PX80		0x7114
 #define ST_M25PX16		0x7115
 #define ST_M25PX32		0x7116