Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/38833 )
Change subject: sb600spi: Add spireadmode ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/flashrom/+/38833/1/sb600spi.c File sb600spi.c:
https://review.coreboot.org/c/flashrom/+/38833/1/sb600spi.c@451 PS1, Line 451: (amd_gen < CHIPSET_BOLTON))
Looking at the code below again, it seems that spireadmode does not have an effect for chipsets < Bo […]
Done
https://review.coreboot.org/c/flashrom/+/38833/1/sb600spi.c@509 PS1, Line 509: if (spispeed_idx >= 0 && set_speed(dev, spispeed_idx) != 0) { : return 1; : } : return 0;
Well, the previous code defaulted to 3, so it never barfed. Still, I would consider it an error. […]
set_speed only writes to the register for setting the speed. Skipping this is intentional. The assumption is that the firmware should have already configured the optimal spi speed, so just default to leaving it unchanged for >= BOLTON. I added a warning for both spireadmode and spispeed when they are left unset.