Attention is currently required from: Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/59072 )
Change subject: dummyflasher: add SR2 emulation harness ......................................................................
Patch Set 18:
(2 comments)
File dummyflasher.c:
https://review.coreboot.org/c/flashrom/+/59072/comment/8f272bc0_278d9f64 PS16, Line 339: data->emu_status[0] &= ro_bits;
WIP was RO before, old code is: […]
And what does that tell us about the state of WIP after that line? AFAICT, it was always cleared here. Does it matter? I guess no, but I had to investigate (check all accesses to `emu_status` basically). It's just so much nicer to investigate such things for dedicated commits :) I guess changing this single line, no matter how minor it seems, makes about 50% of the review of this change (and it's not a small change).
https://review.coreboot.org/c/flashrom/+/59072/comment/433daacc_c06c9d76 PS16, Line 347: other chips might differ
At least datasheet for W25Q128FV claims otherwise in its note on previous generations: […]
So we actually know already that chips with different behavior exist. That's already more information than the comment provides :) If that is the reason for the comment, please rephrase.
Anyway, what I meant is that there can always be chips that act differently. That's the case for WRSR, but also for WRSR2, and also, less likely, for read/write/erase commands.