Shiyu Sun has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/48662 ) Change subject: realtek_mst_i2c_spi.c: Add ISP mode check ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/flashrom/+/48662/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/flashrom/+/48662/3//COMMIT_MSG@13 PS3, Line 13: TEST=build and run mst commands
Test your changes each time you revise the patch otherwise this line isn't valid. I believe I did try this for every change I have made. Build, copy to DUT and test with multiple commands.
https://review.coreboot.org/c/flashrom/+/48662/3/realtek_mst_i2c_spi.c File realtek_mst_i2c_spi.c: https://review.coreboot.org/c/flashrom/+/48662/3/realtek_mst_i2c_spi.c@124 PS3, Line 124: MCU_ISP_MODE_MASK, MCU_ISP_MODE_MASK
this isn't right, you have mask used for the target. I believe we are waiting for the bit 7 to reach 1 so we do expect to have '(val & MCU_ISP_MODE_MASK) = MCU_ISP_MODE_MASK' as the enter ISP success. Does it means I have to use 0x80 directly here?
-- To view, visit https://review.coreboot.org/c/flashrom/+/48662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib1ab8370eb6335a77bb293fc98a8ab7be465db4f Gerrit-Change-Number: 48662 Gerrit-PatchSet: 3 Gerrit-Owner: Shiyu Sun <sshiyu@google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 18 Dec 2020 06:47:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Edward O'Callaghan <quasisec@chromium.org> Gerrit-MessageType: comment