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[XS] Change in flashrom[main]: meson: Fix project name as flashrom
by Anastasia Klimchuk (Code Review) 23 Jul '24

23 Jul '24

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/83611?usp=email ) Change subject: meson: Fix project name as flashrom ...................................................................... meson: Fix project name as flashrom Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/83611 Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M meson.build 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Peter Marheine: Looks good to me, approved build bot (Jenkins): Verified diff --git a/meson.build b/meson.build index 458b6e8..ae56b26 100644 --- a/meson.build +++ b/meson.build @@ -1,4 +1,4 @@ -project('flashromutils', 'c', +project('flashrom', 'c', version : run_command('cat', 'VERSION', check: true).stdout().strip(), license : 'GPL-2.0', meson_version : '>=0.56.0', -- To view, visit https://review.coreboot.org/c/flashrom/+/83611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a Gerrit-Change-Number: 83611 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in flashrom[main]: meson: Fix project name as flashrom
by Peter Marheine (Code Review) 23 Jul '24

23 Jul '24

Attention is currently required from: Anastasia Klimchuk. Peter Marheine has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83611?usp=email ) Change subject: meson: Fix project name as flashrom ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a Gerrit-Change-Number: 83611 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Tue, 23 Jul 2024 06:41:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in flashrom[main]: meson: Fix project name as flashrom
by Anastasia Klimchuk (Code Review) 23 Jul '24

23 Jul '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83611?usp=email ) Change subject: meson: Fix project name as flashrom ...................................................................... meson: Fix project name as flashrom Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M meson.build 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/11/83611/1 diff --git a/meson.build b/meson.build index 458b6e8..ae56b26 100644 --- a/meson.build +++ b/meson.build @@ -1,4 +1,4 @@ -project('flashromutils', 'c', +project('flashrom', 'c', version : run_command('cat', 'VERSION', check: true).stdout().strip(), license : 'GPL-2.0', meson_version : '>=0.56.0', -- To view, visit https://review.coreboot.org/c/flashrom/+/83611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I08785283a62c21491ac633f6fed43a7dc3fd825a Gerrit-Change-Number: 83611 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 22 Jul '24

22 Jul '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/83584?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: doc: Add overview doc for user_docs ...................................................................... doc: Add overview doc for user_docs This document is converted from Technology page on wiki https://wiki.flashrom.org/Technology Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M doc/intro.rst A doc/user_docs/Amd_am29f010_tsop32.jpg A doc/user_docs/Bios_savior.jpg A doc/user_docs/Dip32_chip.jpg A doc/user_docs/Dip32_chip_back.jpg A doc/user_docs/Dip32_in_socket.jpg A doc/user_docs/Dip8_chip.jpg A doc/user_docs/Dip8_chip_back.jpg A doc/user_docs/Dip8_in_socket.jpg A doc/user_docs/Dip_tool.jpg A doc/user_docs/Dual_plcc32_soldered.jpg A doc/user_docs/Empty_dip32_socket.jpg A doc/user_docs/Empty_dip8_socket.jpg A doc/user_docs/Empty_plcc32_socket.jpg A doc/user_docs/Flash-BGA.jpg A doc/user_docs/Plcc32_chip.jpg A doc/user_docs/Plcc32_chip_back.jpg A doc/user_docs/Plcc32_in_socket.jpg A doc/user_docs/Plcc_tool.jpg A doc/user_docs/Pushpin_roms_2.jpg A doc/user_docs/Soic8_chip.jpg A doc/user_docs/Soic8_socket_back.jpg A doc/user_docs/Soic8_socket_front_closed.jpg A doc/user_docs/Soic8_socket_half_opened.jpg A doc/user_docs/Soic8_socket_open.jpg A doc/user_docs/Soic8_socket_with_chip.jpg A doc/user_docs/Soic8_socket_with_chip_inserted.jpg A doc/user_docs/Soldered_plcc32.jpg A doc/user_docs/Soldered_tsop40.jpg A doc/user_docs/Soldered_tsop48.jpg A doc/user_docs/Spi-socket-dscn2913-1024x768.jpg A doc/user_docs/Sst_39vf040_tsop32.jpg A doc/user_docs/Top_hat_flash.jpeg M doc/user_docs/index.rst A doc/user_docs/overview.rst 35 files changed, 303 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/83584/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Anastasia Klimchuk (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Bora Guvendik, DZ, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. Anastasia Klimchuk has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (3 comments) Patchset: PS3: > OK, I will review this patch in next week. Thank you so much for your help! I will close this comment thread. PS3: > Yes I was asking in the other comment earlier, if it's possible to send datasheet to me (e.g. […] I am closing this comment thread, since the review is now in progress. File flashchips.c: https://review.coreboot.org/c/flashrom/+/82626/comment/af24a885_9210826f?us… : PS3, Line 11620: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, > There is only one status register in this Flash. So, it doesn't need to define the […] Thank you for explanation! I see, no need for any of FEATURE_WRSR2 or FEATURE_WRSR3 etc. It's a good idea to add `FEATURE_CFGR` anyway, but if reg_bits need configuration register then it would be required to add `FEATURE_CFGR`. -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 09:29:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: DZ <danielzhang(a)mxic.com.cn> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by DZ (Code Review) 22 Jul '24

22 Jul '24

Attention is currently required from: Anastasia Klimchuk, Bora Guvendik, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. DZ has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (1 comment) File flashchips.c: https://review.coreboot.org/c/flashrom/+/82626/comment/3a173bad_52e97320?us… : PS3, Line 11620: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, > How many bytes status register has? Perhaps it should be defined with `FEATURE_WRSR_EXT2` and/or `FE […] There is only one status register in this Flash. So, it doesn't need to define the FEATURE_WRSR_EXT2 or FEATURE_WRSR_EXT3. And it has only one configuration register in the Flash, user can add FEATURE_CFGR label in .feature_bits field if needed. -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Mon, 22 Jul 2024 04:01:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: DZ <danielzhang(a)mxic.com.cn> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org>

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[M] Change in flashrom[main]: flashchips: add support for chip model Winbond W25Q32JV_M
by Michael Heimpold (Code Review) 21 Jul '24

21 Jul '24

Michael Heimpold has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83586?usp=email ) Change subject: flashchips: add support for chip model Winbond W25Q32JV_M ...................................................................... flashchips: add support for chip model Winbond W25Q32JV_M This is a 4 MiB model with QE=0 factory setting. Tested with ch341a programmer: probe, read, write, erase Link to datasheet: https://www.winbond.com/resource-files/W25Q32JV%20RevI%2005042021%20Plus.pdf Change-Id: I374c466848eabf5647dc88e016ac32b99ec37a06 Signed-off-by: Michael Heimpold <mhei(a)heimpold.de> --- M flashchips.c M include/flashchips.h 2 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/83586/1 diff --git a/flashchips.c b/flashchips.c index 1a7954c..d61fe56 100644 --- a/flashchips.c +++ b/flashchips.c @@ -19879,6 +19879,58 @@ { .vendor = "Winbond", + .name = "W25Q32JV_M", + .bustype = BUS_SPI, + .manufacture_id = WINBOND_NEX_ID, + .model_id = WINBOND_NEX_W25Q32JV_M, + .total_size = 4096, + .page_size = 256, + /* supports SFDP */ + /* OTP: 3x 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | + FEATURE_WRSR2 | FEATURE_WRSR3, + .tested = TEST_OK_PREW, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 1024} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 128} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 64} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {4 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, + .unlock = SPI_DISABLE_BLOCKPROTECT, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .sec = {STATUS1, 6, RW}, + .tb = {STATUS1, 5, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .cmp = {STATUS2, 6, RW}, + .srl = {STATUS2, 0, RW}, + .wps = {STATUS3, 2, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "Winbond", .name = "W25Q32JV", .bustype = BUS_SPI, .manufacture_id = WINBOND_NEX_ID, diff --git a/include/flashchips.h b/include/flashchips.h index a43a0f9..a85c3bf 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -1012,6 +1012,7 @@ #define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */ #define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */ #define WINBOND_NEX_W25Q16JV_M 0x7015 /* W25Q16JV_M (QE=0) */ +#define WINBOND_NEX_W25Q32JV_M 0x7016 /* W25Q32JV_M (QE=0) */ #define WINBOND_NEX_W25Q64JV 0x7017 /* W25Q64JV */ #define WINBOND_NEX_W25Q128_V_M 0x7018 /* W25Q128JVSM */ #define WINBOND_NEX_W25Q256JV_M 0x7019 /* W25Q256JV_M (QE=0) */ -- To view, visit https://review.coreboot.org/c/flashrom/+/83586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I374c466848eabf5647dc88e016ac32b99ec37a06 Gerrit-Change-Number: 83586 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Heimpold <mhei(a)heimpold.de>

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[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 21 Jul '24

21 Jul '24

Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/83584?usp=email ) Change subject: doc: Add overview doc for user_docs ...................................................................... Patch Set 1: (1 comment) File doc/user_docs/overview.rst: https://review.coreboot.org/c/flashrom/+/83584/comment/1f112f1f_165b5e02?us… : PS1, Line 188: :doc:`in-system` the doc is in CB:83451 -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 21 Jul 2024 06:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in flashrom[main]: doc: Add overview doc for user_docs
by Anastasia Klimchuk (Code Review) 20 Jul '24

20 Jul '24

Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/83584?usp=email ) Change subject: doc: Add overview doc for user_docs ...................................................................... doc: Add overview doc for user_docs This document is converted from Technology page on wiki https://wiki.flashrom.org/Technology Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- A doc/user_docs/Amd_am29f010_tsop32.jpg A doc/user_docs/Bios_savior.jpg A doc/user_docs/Dip32_chip.jpg A doc/user_docs/Dip32_chip_back.jpg A doc/user_docs/Dip32_in_socket.jpg A doc/user_docs/Dip8_chip.jpg A doc/user_docs/Dip8_chip_back.jpg A doc/user_docs/Dip8_in_socket.jpg A doc/user_docs/Dip_tool.jpg A doc/user_docs/Dual_plcc32_soldered.jpg A doc/user_docs/Empty_dip32_socket.jpg A doc/user_docs/Empty_dip8_socket.jpg A doc/user_docs/Empty_plcc32_socket.jpg A doc/user_docs/Flash-BGA.jpg A doc/user_docs/Plcc32_chip.jpg A doc/user_docs/Plcc32_chip_back.jpg A doc/user_docs/Plcc32_in_socket.jpg A doc/user_docs/Plcc_tool.jpg A doc/user_docs/Pushpin_roms_2.jpg A doc/user_docs/Soic8_chip.jpg A doc/user_docs/Soic8_socket_back.jpg A doc/user_docs/Soic8_socket_front_closed.jpg A doc/user_docs/Soic8_socket_half_opened.jpg A doc/user_docs/Soic8_socket_open.jpg A doc/user_docs/Soic8_socket_with_chip.jpg A doc/user_docs/Soic8_socket_with_chip_inserted.jpg A doc/user_docs/Soldered_plcc32.jpg A doc/user_docs/Soldered_tsop40.jpg A doc/user_docs/Soldered_tsop48.jpg A doc/user_docs/Spi-socket-dscn2913-1024x768.jpg A doc/user_docs/Sst_39vf040_tsop32.jpg A doc/user_docs/Top_hat_flash.jpeg M doc/user_docs/index.rst A doc/user_docs/overview.rst 34 files changed, 302 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/84/83584/1 diff --git a/doc/user_docs/Amd_am29f010_tsop32.jpg b/doc/user_docs/Amd_am29f010_tsop32.jpg new file mode 100644 index 0000000..faf0982 --- /dev/null +++ b/doc/user_docs/Amd_am29f010_tsop32.jpg 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a/doc/user_docs/Sst_39vf040_tsop32.jpg b/doc/user_docs/Sst_39vf040_tsop32.jpg new file mode 100644 index 0000000..beefeba --- /dev/null +++ b/doc/user_docs/Sst_39vf040_tsop32.jpg Binary files differ diff --git a/doc/user_docs/Top_hat_flash.jpeg b/doc/user_docs/Top_hat_flash.jpeg new file mode 100644 index 0000000..8edd27e --- /dev/null +++ b/doc/user_docs/Top_hat_flash.jpeg Binary files differ diff --git a/doc/user_docs/index.rst b/doc/user_docs/index.rst index b61567a..4be71bb 100644 --- a/doc/user_docs/index.rst +++ b/doc/user_docs/index.rst @@ -4,6 +4,7 @@ .. toctree:: :maxdepth: 1 + overview fw_updates_vs_spi_wp example_partial_wp chromebooks diff --git a/doc/user_docs/overview.rst b/doc/user_docs/overview.rst new file mode 100644 index 0000000..1b3fe40 --- /dev/null +++ b/doc/user_docs/overview.rst @@ -0,0 +1,301 @@ +========== +Overview +========== + +Modern mainboards store the BIOS in a reprogrammable flash chip. +There are hundreds of different flash (`EEPROM <https://en.wikipedia.org/wiki/EEPROM>`_) chips, +with variables such as memory size, speed, communication bus (Parallel, LPC, FWH, SPI) and packaging to name just a few. + +Packaging/housing/form factor +============================= + +DIP32: Dual In-line Package, 32 pins +------------------------------------ + +DIP32 top + +.. image:: Dip32_chip.jpg + :alt: DIP32 top + +DIP32 bottom + +.. image:: Dip32_chip_back.jpg + :alt: DIP32 bottom + +DIP32 in a socket + +.. image:: Dip32_in_socket.jpg + :alt: DIP32 in a socket + +DIP32 socket + +.. image:: Empty_dip32_socket.jpg + :alt: DIP32 socket + +DIP32 extractor tool + +.. image:: Dip_tool.jpg + :alt: DIP32 extractor tool + +A rectangular black plastic block with 16 pins along each of the two longer sides of the package +(32 pins in total). DIP32 chips can be socketed which means they are detachable from the mainboard +using physical force. If they haven't been moved in and out of the socket very much, +they can appear to be quite difficult to release from the socket. One way to remove a DIP32 chip +from a socket is by prying a **thin screwdriver** in between the plastic package and the socket, +along the shorter sides where there are no pins, and then gently bending the screwdriver to push +the chip upwards, away from the mainboard. Alternate between the two sides to avoid bending the pins, +and don't touch any of the pins with the screwdriver (search about ESD, electro-static discharge). +If the chip is **soldered directly to the mainboard**, it has to be desoldered in order to be +reprogrammed outside the mainboard. If you do this, it's a good idea to +`solder a socket to the mainboard <http://www.coreboot.org/Soldering_a_socket_on_your_board>`_ instead, +to ease any future experiments. + +PLCC32: Plastic Leaded Chip Carrier, 32 pins +-------------------------------------------- + +PLCC32 top + + .. image:: Plcc32_chip.jpg + :alt: PLCC32 top + +PLCC32 botto + + .. image:: Plcc32_chip_back.jpg + :alt: PLCC32 bottom + +PLCC32 socket + + .. image:: Plcc32_in_socket.jpg + :alt: PLCC32 socket + +PLCC32 in a socket + + .. image:: Empty_plcc32_socket.jpg + :alt: PLCC32 in a socket + +Soldered PLCC3 + + .. image:: Soldered_plcc32.jpg + :alt: Soldered PLCC32 + +Two soldered PLCC32 + + .. image:: Dual_plcc32_soldered.jpg + :alt: Two soldered PLCC32 + +PLCC32 Bios Savior + + .. image:: Bios_savior.jpg + :alt: PLCC32 Bios Savior + +PLCC32 Top-Hat-Flash adapte + + .. image:: Top_hat_flash.jpeg + :alt: PLCC32 Top-Hat-Flash adapter + +PLCC32 pushpin trick + + .. image:: Pushpin_roms_2.jpg + :alt: PLCC32 pushpin trick + +PLCC extractor tool + + .. image:: Plcc_tool.jpg + :alt: PLCC extractor tool + +Black plastic block again, but this one is much more square. +PLCC32 was becoming the standard for mainboards after DIP32 chips because of its smaller physical size. +PLCC can also be **socketed** or **soldered directly to the mainboard**. +Socketed PLCC32 chips can be removed using a special PLCC removal tool, +or using a piece of nylon line tied in a loop around the chip and pulled swiftly straight up, +or bending/prying using small screwdrivers if one is careful. PLCC32 sockets are often fragile +so the screwdriver approach is not recommended. While the nylon line method sounds strange it works well. +Desoldering PLCC32 chips and soldering on a socket can be done using either a desoldering station +or even just a heat gun. You can also cut the chip with a sharp knife, **but it will be destroyed in the process, of course**. + +DIP8: Dual In-line Package, 8 pins +---------------------------------- + +DIP8 top + + .. image:: Dip8_chip.jpg + :alt: DIP8 top + +DIP8 bottom + + .. image:: Dip8_chip_back.jpg + :alt: DIP8 bottom + +DIP8 in a socket + + .. image:: Dip8_in_socket.jpg + :alt: DIP8 in a socket + +DIP8 socket + + .. image:: Empty_dip8_socket.jpg + :alt: DIP8 socket + +Most recent boards use DIP8 chips (which always employ the SPI protocol) or SO8/SOIC8 chips (see below). +DIP8 chips are always **socketed**, and can thus be easily removed (and hot-swapped), +for example using a small screwdriver. This allows for relatively simple recovery in case of an incorrectly flashed chip. + +SO8/SOIC8: Small-Outline Integrated Circuit, 8 pins +--------------------------------------------------- + +Soldered SOIC8 + + .. image:: Soic8_chip.jpg + :alt: Soldered SOIC8 + +SOIC8 socket, front, closed + + .. image:: Soic8_socket_front_closed.jpg + :alt: SOIC8 socket, front, closed + +SOIC8 socket, half open + + .. image:: Soic8_socket_half_opened.jpg + :alt: SOIC8 socket, half open + +SOIC8 socket, open + + .. image:: Soic8_socket_open.jpg + :alt: SOIC8 socket, open + +SOIC8 socket, back + + .. image:: Soic8_socket_back.jpg + :alt: SOIC8 socket, back + +SOIC8 socket, chip nearby + + .. image:: Soic8_socket_with_chip.jpg + :alt: SOIC8 socket, chip nearby + +SOIC8 socket, chip inserted + + .. image:: Soic8_socket_with_chip_inserted.jpg + :alt: SOIC8 socket, chip inserted + +Another type of SOIC8 adapter + + .. image:: Spi-socket-dscn2913-1024x768.jpg + :alt: Another type of SOIC8 adapter + +Similarly to the DIP8 chips, these always use the SPI protocol. +However, SO8/SOIC8 chips are most often soldered onto the board directly without a socket. +In that case a few boards have a header to allow :doc:`in-system`. You can also desolder +a soldered SO8 chip and solder an SO8 socket/adapter in its place, or build +a `SOIC-to-DIP adapter <http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/>`_. +Some of the cheapest SOIC ZIF sockets are made by `Wieson <https://www.wieson.com/go/en/wieson/index.php?lang=en>`_. +They have 3 models available - G6179-10(0000), G6179-20(0000) and a 16 pin version named G6179-07(0000). +They are available for example from `siliconkit <https://siliconkit.com/oc3/>`_, +`Dediprog <https://www.dediprog.com/>`_, as well as `alibaba <http://alibaba.com/>`_. +For the usual "BIOS" flash chips you want the G6179-10 model (look also for G6179-100000). +Dediprog usually has them or similar ones as well but has steep shipping costs and an unpractical minimum order quantity. + +TSOP: Thin Small-Outline Package, 32, 40, or 48 pins +---------------------------------------------------- + +Soldered TSOP32 + + .. image:: Amd_am29f010_tsop32.jpg + :alt: Soldered TSOP32 + +Soldered TSOP32 + + .. image:: Sst_39vf040_tsop32.jpg + :alt: Soldered TSOP32 + +Soldered TSOP40 + + .. image:: Soldered_tsop40.jpg + :alt: Soldered TSOP40 + +Soldered TSOP48 + + .. image:: Soldered_tsop48.jpg + :alt: Soldered TSOP48 + +TSOPs are often used in embedded systems where size is important and there is no need +for replacement in the field. It is possible to (de)solder TSOPs by hand, +but it's not trivial and a reasonable amount of soldering skills are required. + +BGA: Ball Grid Array +-------------------- + +BGA package flash + + .. image:: Flash-BGA.jpg + :alt: BGA package flash + +BGAs are often used in embedded systems where size is important and there is no need +for replacement in the field. It is not easily possible to (de)solder BGA by hand. + +Communication bus protocol +========================== + +There are four major communication bus protocols for flash chips, +each with multiple subtle variants in the command set: + +* **SPI**: Serial Peripheral Interface, introduced ca. 2006. +* **Parallel**: The oldest flash bus, phased out on mainboards around 2002. +* **LPC**: Low Pin Count, a standard introduced ca. 1998. +* **FWH**: Firmware Hub, a variant of the LPC standard introduced at the same time. + FWH is a special case variant of LPC with one bit set differently in the memory read/write commands. + That means some data sheets mention the chips speak LPC although + they will not respond to regular LPC read/write cycles. + +Here's an attempt to create a marketing language -> chip type mapping: + +* JEDEC Flash -> Parallel (well, mostly) +* FWH -> FWH +* Firmware Hub -> FWH +* LPC Firmware -> FWH +* Firmware Memory -> FWH +* Low Pin Count (if Firmware/FWH is not mentioned) -> LPC +* LPC (if Firmware is not mentioned) -> LPC +* Serial Flash -> SPI + +SST data sheets have the following conventions: + +* LPC Memory Read -> LPC +* Firmware Memory Read -> FWH + +If both are mentioned, the chip supports both. + +If you're not sure about whether a device is LPC or FWH, look at the read/write cycle definitions. + +FWH + +=========== ========== ============== ========================================================== +Clock Cycle Field Name Field contents Comments +=========== ========== ============== ========================================================== +1 START 1101/1110 1101 for READ, 1110 for WRITE. +2 IDSEL 0000 to 1111 IDSEL value to be shifted out to the chip. +3-9 IMADDR YYYY The address to be read/written. 7 cycles total == 28 bits. +10+ ... ... ... +=========== ========== ============== ========================================================== + +LPC + +=========== =================== ============== ========================================================== +Clock Cycle Field Name Field contents Comments +=========== =================== ============== ========================================================== +1 START 0000 ... +2 CYCLETYPE+DIRECTION 010X/011X 010X for READ, 011X for WRITE. X means "reserved". +3-10 ADDRESS YYYY The address to be read/written. 8 cycles total == 32 bits. +11+ ... ... ... +=========== =================== ============== ========================================================== + +Generally, a parallel flash chip will not speak any other protocols. +SPI flash chips also don't speak any other protocols. +LPC flash chips sometimes speak FWH as well and vice versa, +but they will not speak any protocols besides LPC/FWH. + +Hardware Redundancy +=================== +Gigabyte's DualBios: http://www.google.com/patents/US6892323 + +ASUS: http://www.google.com/patents/US8015449 -- To view, visit https://review.coreboot.org/c/flashrom/+/83584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I93107d6b5530c301dd90f7177758632d9d1810eb Gerrit-Change-Number: 83584 Gerrit-PatchSet: 1 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org>

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[S] Change in flashrom[main]: flashchips: add support for MX77U51250F chip
by Anastasia Klimchuk (Code Review) 20 Jul '24

20 Jul '24

Attention is currently required from: Bora Guvendik, DZ, Nikolai Artemiev, Stefan Reinauer, Subrata Banik. Anastasia Klimchuk has posted comments on this change by Bora Guvendik. ( https://review.coreboot.org/c/flashrom/+/82626?usp=email ) Change subject: flashchips: add support for MX77U51250F chip ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/82626/comment/53b95ded_c4afbc6e?us… : PS3, Line 10: Please add test information in commit message. Specifically, which programmer you are using (if that is internal, then which board was it on). Also which operations have you tested. From the other comment, if you are testing write-protect, also mention which exactly operations you were testing for wp. Thank you! File flashchips.c: https://review.coreboot.org/c/flashrom/+/82626/comment/bd199659_1790d1b1?us… : PS3, Line 11618: 65536 > we might need to fake this part to show the max capacity is 32MB I think this kind of custom adjustments should be added to ChromeOS fork (which is I assume what you meant to say, but I just want to be clear). I fully understand the idea to speed up flashing if you only happen to use half of available capacity. But if this flash has 64MB size, it should be defined like this in the flashchip definition. We have users around the world, and upstream definition should correctly describe the features of the chip model. https://review.coreboot.org/c/flashrom/+/82626/comment/170295c4_aa379a58?us… : PS3, Line 11620: .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA, > In the datasheet, this Flash doesn't support FEATURE_WRSR2, FEATURE_WRSR3. How many bytes status register has? Perhaps it should be defined with `FEATURE_WRSR_EXT2` and/or `FEATURE_WRSR_EXT3` ? It depends on whether you can only write the whole status register (all bytes at the same time), or you can write each byte independently. https://review.coreboot.org/c/flashrom/+/82626/comment/98f8f88d_09500662?us… : PS3, Line 11648: }, > OK, thank you for providing these backgroud information. If you plan to add write-protect support (i.e. define reg_bits), you also need to test it , and mark test status accordingly. Current test status TEST_OK_PREW indicates that write-protect is not tested. If you test it successfully, then test status should be updated to TEST_OK_PREWB -- To view, visit https://review.coreboot.org/c/flashrom/+/82626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c Gerrit-Change-Number: 82626 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: DZ <danielzhang(a)mxic.com.cn> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: DZ <danielzhang(a)mxic.com.cn> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Sat, 20 Jul 2024 09:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: DZ <danielzhang(a)mxic.com.cn> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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