Attention is currently required from: Aarya, Nikolai Artemiev, Sergii Dmytruk.
Anastasia Klimchuk has uploaded a new patch set (#5) to the change originally created by Sergii Dmytruk. ( https://review.coreboot.org/c/flashrom/+/84102?usp=email )
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: Complete and fix progress feature implementation for all operations
......................................................................
Complete and fix progress feature implementation for all operations
Original progress reporting implemented in CB:49643 and it has some
issues, for example:
size_t start_address = start;
size_t end_address = len - start;
End address is anything but length minus start address.
update_progress(flash,
FLASHROM_PROGRESS_READ,
/*current*/ start - start_address + to_read,
/*total*/ end_address);
Total should just be length if that's how current value is computed.
---
libflashrom needs to know total size ahead of time.
That's init_progress() and changed update_progress().
It also needs to store the last current value to be able to update it.
That's stage_progress in flashrom_flashctx.
Measuring accurately amount of data which will be read/erased/written
isn't easy because things can be skipped as optimizations. The next
patch in the chain aims to address this, there are TODO/FIXME
comments there.
---
CLI shares terminal with the rest of the code and has to maintain more
state to handle that reasonably well.
The progress doesn't just dump lots of stuff on the screen which
probably won't fly because of CB:64668, but it's not hard to adjust
this.
---
A script to test the CLI:
\#!/bin/bash
t=${1:-rewW}
shift
if [[ $t =~ r ]]; then
echo ">>> READ"
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -r dump.rom --progress "$@"
echo
fi
if [[ $t =~ e ]]; then
echo ">>> ERASE"
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -E --progress "$@"
echo
fi
if [[ $t =~ w ]]; then
echo ">>> WRITE (without erase)"
dd if=/dev/zero of=zero.rom bs=1M count=16 2> /dev/null
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz -w zero.rom --progress "$@"
echo
fi
if [[ $t =~ W ]]; then
echo ">>> WRITE (with erase)"
dd if=/dev/zero of=zero.rom bs=1M count=16 2> /dev/null
dd if=/dev/random of=random.rom bs=1M count=16 2> /dev/null
./flashrom -p dummy:emulate=W25Q128FV,freq=64mhz,image=random.rom -w zero.rom --progress "$@"
echo
fi
Co-developed-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Co-developed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Change-Id: If1e40fc97f443c4f0c0501cef11cff1f3f84c051
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M 82802ab.c
M at45db.c
M cli_classic.c
M cli_output.c
M dediprog.c
M doc/release_notes/devel.rst
M en29lv640b.c
M erasure_layout.c
M flashrom.c
M include/flash.h
M it87spi.c
M jedec.c
M libflashrom.c
M linux_mtd.c
M parade_lspcon.c
M realtek_mst_i2c_spi.c
M spi.c
M spi25.c
M sst28sf040.c
M tests/chip.c
M tests/spi25.c
M tests/tests.c
M tests/tests.h
23 files changed, 285 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/02/84102/5
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Anastasia Klimchuk has posted comments on this change by Sergii Dmytruk. ( https://review.coreboot.org/c/flashrom/+/84102?usp=email )
Change subject: Complete and fix progress feature implementation for all operations
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/84102/comment/978b236f_e60fad00?us… :
PS1, Line 46:
: CLI shares terminal with the rest of the code
> I just meant that flashrom can print log output at any point (like it prints `DONE something`) so CL […]
Thanks, I got it now. I made other comment in the code, on this topic.
File cli_output.c:
https://review.coreboot.org/c/flashrom/+/84102/comment/27f746c1_498ea1c8?us… :
PS4, Line 119: 16 * FLASHROM_PROGRESS_NR
These would be 48? And then 2 backspaces each time, so 92 backspaces?
The output of one callback is max 5chars stage name + space + 2 digits + % sign + ... and that's 12 chars max?
Why do you need 92 backspaces? Maybe I misunderstand something
Does this relate to the part in commit message:
> The progress doesn't just dump lots of stuff on the screen which
probably won't fly because of CB:64668, but it's not hard to adjust
this.
I read the linked patch, it seems the concern was that if you try to delete previous stage of progress, you can accidentally delete some other messages. But the concern is still valid right?
File include/flash.h:
https://review.coreboot.org/c/flashrom/+/84102/comment/e6eb187b_66cd178c?us… :
PS1, Line 544: struct stage_progress {
: size_t current;
: size_t total;
: };
> This is not part of API, nothing in `libflashrom.h` uses this structure.
Acknowledged
https://review.coreboot.org/c/flashrom/+/84102/comment/2ec83f84_35c0d0bd?us… :
PS1, Line 587: struct stage_progress stage_progress[FLASHROM_PROGRESS_NR];
> That would change API and ABI. […]
I think (I think) I understand. From the point of view of libflashrom user, the user enables the progress flag, sets progress callback (maybe with custom user_data), and then just runs whatever operations are needed. So the user controls the callback, but all the information needed for the callback is already contained in flashrom_progress.
Is this correct?
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Attention is currently required from: Bill XIE, Nikolai Artemiev.
Hello Bill XIE, Nikolai Artemiev, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84567?usp=email
to look at the new patch set (#2).
Change subject: ichspi: Change the opcode position for reprogramming on the fly 2->4
......................................................................
ichspi: Change the opcode position for reprogramming on the fly 2->4
The function for reprogramming on the fly was using the default
configuration O_ST_M25P as a base and the position 2 as the position
to reprogram. Position 2 corresponds to JEDEC_SE which is often useful
for chip erase (when less than whole chip needs to be erased).
This patch changes the default position to reprogram to 4, which
corresponds to JEDEC_REMS. It is used less often, but if it needs to
be used, it will be discovered missing and reprogrammed back.
For erase opcodes, there is usually several of them available. So if
one is missing, erase still can be performed with the remaining ones.
However, this hides the fact that one of available erase opcodes is
missing (it won't be reprogrammed back), and also it gives non-optimal
erase layout.
Context: https://ticket.coreboot.org/issues/556
Change-Id: I6bc855daedf0af2e8de191f23a3512de3ebc3fef
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M ichspi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/84567/2
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Anastasia Klimchuk has posted comments on this change by Bill XIE. ( https://review.coreboot.org/c/flashrom/+/84253?usp=email )
Change subject: ichspi: Restore Sector erase opcode after send command
......................................................................
Patch Set 1:
(2 comments)
File ichspi.c:
https://review.coreboot.org/c/flashrom/+/84253/comment/28a8b295_4d4dbfde?us… :
PS1, Line 664: int oppos = 2; // use original JEDEC_BE_D8 offset
I made a separate patch CB:84567 in case it end up being useful.
> It's worth noting that newer CPUs don't support this code path (they use hwseq)
Oh, maybe that partially explains why the issue was not noticed before...
https://review.coreboot.org/c/flashrom/+/84253/comment/739b62fa_a396c952?us… :
PS1, Line 1843:
: static bool ich_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode)
: {
: return find_opcode(curopcodes, opcode) >= 0;
> Rather than restoring JEDEC_SE after every ich_spi_send_command() call, we could add a check here to […]
Oh this is really clever solution :) Thank you!
If we go that way, we can treat other erase opcodes in the same way? Specifically, in the POSSIBLE_OPCODES there are:
JEDEC_SE
JEDEC_BE_52
JEDEC_BE_D8
JEDEC_CE_C7
Maybe we can add the check here for all those?
Bill, would you agree to change your patch, and test the different solution?
As a plan B I can upload new version of the patch, but asking you first because you are the author (and you did all the debugging).
Also, in any case, original author of the patch stays (even if someone uploads new version)
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Anastasia Klimchuk has posted comments on this change by Anastasia Klimchuk. ( https://review.coreboot.org/c/flashrom/+/84567?usp=email )
Change subject: ichspi: Change the opcode position for reprogramming on the fly 2->4
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Needs to be tested
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Anastasia Klimchuk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/84567?usp=email )
Change subject: ichspi: Change the opcode position for reprogramming on the fly 2->4
......................................................................
ichspi: Change the opcode position for reprogramming on the fly 2->4
The function for reprogramming on the fly was using the default
configuration O_ST_M25P as a base and the position 2 as the position
to reprogram. Position 2 corresponds to JEDEC_SE which is often useful
for chip erase (when less than whole chip needs to be erased).
This patch changes the default position to reprogram to 4, which
corresponds to JEDEC_REMS. It is used less often, but if it needs to
be used, it will be discovered missing and reprogrammed back.
For erase opcodes, there is usually several of them available. So if
one is missing, erase still can be performed with the remaining ones.
However, this hides the fact that one of available erase opcodes is
missing (it won't be reprogrammed back), and also it gives non-optimal
erase layout.
Change-Id: I6bc855daedf0af2e8de191f23a3512de3ebc3fef
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M ichspi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/67/84567/1
diff --git a/ichspi.c b/ichspi.c
index d01f2f3..358d9f4 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -661,7 +661,7 @@
else // we have an invalid case
return SPI_INVALID_LENGTH;
}
- int oppos = 2; // use original JEDEC_BE_D8 offset
+ int oppos = 4; // use the original position of JEDEC_REMS
curopcodes->opcode[oppos].opcode = opcode;
curopcodes->opcode[oppos].spi_type = spi_type;
program_opcodes(curopcodes, 0, ich_generation);
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Peter Marheine has posted comments on this change by Peter Marheine. ( https://review.coreboot.org/c/flashrom/+/84557?usp=email )
Change subject: build: never install cmocka
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> This is great, thank you! […]
Rebased onto main~1, which ought to be enough.
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Anastasia Klimchuk has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/flashrom/+/23053?usp=email )
Change subject: Fwd: Software info for Willem/EZOflash
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> I have a homemade PCB3B variant that was later modified to (apparently proprietary) PCB45 specs, fol […]
Keith, hello! Thank you :) Stay with us, maybe there will be something to test soon.
PS1:
> Sounds great, thank you! […]
Forgot to say: you can push the patch even if it's "work in progress", maybe you want to ask questions, then other people can help!
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Change subject: build: never install cmocka
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
This is great, thank you!
I will look if it's possible to re-run Jenkins, the plan B I will do some small and useful commit, and after submitting this one can be rebased :)
I don't want to "force +1", it's better to make CI re-run
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Hello Anastasia Klimchuk, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/84557?usp=email
to look at the new patch set (#2).
Change subject: build: never install cmocka
......................................................................
build: never install cmocka
meson's default behavior is to install subprojects, so because we use a
wrap to get cmocka if needed and the cmocka wrap sets install=true
unless cross-compiling, cmocka headers and libraries will be installed
by `meson install`. This isn't useful (because cmocka is used only for
tests which don't get installed), and can cause install errors in some
configurations.
meson can be told to never install subprojects with `meson install
--skip-subprojects` which solves this, but is inconvenient because that
option must be specified on the command line and there is little hope of
meson's default behavior changing [1].
To fix this, I've replaced `patch_url` for the wrap with an included
`patch_directory` instead, which was created by unpacking the original
archive pointed to by `patch_url` and setting `install : false` in
src/meson.build.
A more concise option to make the same change would be to make the
change to the `install` option in a new patch specified via `diff_files`
(which works because patches from `diff_files` are applied after
applying the `patch_*` archive), but `diff_files` is not supported by
Meson before version 0.63.0 which would require increasing flashrom's
minimum meson version from the current 0.56.0. This seems too new, since
meson 0.56 was released in October 2020 while meson 0.63 was released in
July 2022.
[1]: https://github.com/mesonbuild/meson/issues/10561#issuecomment-1444059473BUG=https://ticket.coreboot.org/issues/561
Change-Id: I15f549175e2d5d52979814d7f7530da868871ce8
Signed-off-by: Peter Marheine <pmarheine(a)chromium.org>
---
M subprojects/cmocka.wrap
A subprojects/packagefiles/cmocka-1.1.5/LICENSE.build
A subprojects/packagefiles/cmocka-1.1.5/meson.build
A subprojects/packagefiles/cmocka-1.1.5/private/meson.build
A subprojects/packagefiles/cmocka-1.1.5/private_native/meson.build
A subprojects/packagefiles/cmocka-1.1.5/src/meson.build
6 files changed, 325 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/84557/2
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