- flashrom-gerrit - mail.coreboot.org

[L] Change in flashrom[master]: ch347_spi.c: Add initial support for the WCH CH347
by Angel Pons (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Thomas Heijligen, qianfan, Anastasia Klimchuk, Nicholas Chin. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70573 ) Change subject: ch347_spi.c: Add initial support for the WCH CH347 ...................................................................... Patch Set 3: Code-Review+1 (4 comments) File ch347_spi.c: https://review.coreboot.org/c/flashrom/+/70573/comment/d5b9cafa_2aa6e65b PS3, Line 149: command_buf[0] = CH347_CMD_SPI_IN; : command_buf[1] = 4; : command_buf[2] = 0; : command_buf[3] = readcnt & 0xFF; : command_buf[4] = (readcnt & 0xFF00) >> 8; : command_buf[5] = (readcnt & 0xFF0000) >> 16; : command_buf[6] = (readcnt & 0xFF000000) >> 24; Use an initialiser as done in `ch347_set_cs()`? https://review.coreboot.org/c/flashrom/+/70573/comment/a002aee5_c626bbdf PS3, Line 223: -3 nit: spacing here and in the line below https://review.coreboot.org/c/flashrom/+/70573/comment/d7f0def5_20be6950 PS3, Line 222: buff[0] = CH347_CMD_SPI_CFG; : buff[1] = (sizeof(buff)-3) & 0xFF; : buff[2] = ((sizeof(buff)-3) & 0xFF00) >> 8; : /* Not sure what these two bytes do, but the vendor : * drivers seem to unconditionally set these values : */ : buff[5] = 4; : buff[6] = 1; : /* Clock polarity: bit 1 */ : buff[9] = 0; : /* Clock phase: bit 0 */ : buff[11] = 0; : /* Another mystery byte */ : buff[14] = 2; : /* Clock divisor: bits 5:3 */ : buff[15] = (divisor & 0x7) << 3; : /* Bit order: bit 7, 0=MSB */ : buff[17] = 0; : /* Yet another mystery byte */ : buff[19] = 7; : /* CS polarity: bit 7 CS2, bit 6 CS1. 0 = active low */ : buff[24] = 0; Use an initialiser as done in `ch347_set_cs()`? https://review.coreboot.org/c/flashrom/+/70573/comment/634e2f29_91d75e48 PS3, Line 261: 64 * 1024 Where does this come from? -- To view, visit https://review.coreboot.org/c/flashrom/+/70573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba Gerrit-Change-Number: 70573 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alexander Goncharov <chat(a)joursoir.net> Gerrit-CC: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Wed, 21 Dec 2022 10:44:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[L] Change in flashrom[master]: Add initial CH347T SPI programmer
by Angel Pons (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: qianfan, Nicholas Chin, Angel Pons. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70529 ) Change subject: Add initial CH347T SPI programmer ...................................................................... Patch Set 5: (4 comments) File ch347t_spi.c: https://review.coreboot.org/c/flashrom/+/70529/comment/ca704c2c_a8d4666c PS5, Line 94: typedef uint32_t __le32; Why the typedefs? https://review.coreboot.org/c/flashrom/+/70529/comment/699d3264_064dd323 PS5, Line 110: } __attribute__((packed)); This doesn't seem to be portable. https://review.coreboot.org/c/flashrom/+/70529/comment/f4213933_f6424ca9 PS5, Line 169: if (n > CH347_MAX_DATA_WRITE) : n = CH347_MAX_DATA_WRITE; This doesn't seem to be a good idea... https://review.coreboot.org/c/flashrom/+/70529/comment/402d8dca_bf63b31c PS5, Line 279: memset(&csctrl, 0, sizeof(csctrl)); Why not use an initialiser? struct ch347_spi_csctrl_param csctrl = { 0 }; -- To view, visit https://review.coreboot.org/c/flashrom/+/70529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da5e308af76693e60308c8165349128e517e09a Gerrit-Change-Number: 70529 Gerrit-PatchSet: 5 Gerrit-Owner: qianfan <qianfanguijin(a)163.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: qianfan <qianfanguijin(a)163.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Wed, 21 Dec 2022 10:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: flashrom: Check for flash access restrictions in erase path
by Felix Singer (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Edward O'Callaghan, Aarya, Nikolai Artemiev. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70517 ) Change subject: flashrom: Check for flash access restrictions in erase path ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/70517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If027a96a024782c7707c6d38680709a1a117f3ef Gerrit-Change-Number: 70517 Gerrit-PatchSet: 10 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 21 Dec 2022 09:33:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: flashrom: Check for flash access restrictions in erase path
by Edward O'Callaghan (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Felix Singer, Aarya, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70517 ) Change subject: flashrom: Check for flash access restrictions in erase path ...................................................................... Patch Set 10: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/flashrom/+/70517/comment/8b0668f6_6cee66b6 PS9, Line 7: flashrom: Check for flash access restricitons in erase path > typo: restrictions Done -- To view, visit https://review.coreboot.org/c/flashrom/+/70517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If027a96a024782c7707c6d38680709a1a117f3ef Gerrit-Change-Number: 70517 Gerrit-PatchSet: 10 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 21 Dec 2022 09:23:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: flashrom: Check for flash access restrictions in erase path
by Edward O'Callaghan (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Edward O'Callaghan, Aarya, Nikolai Artemiev. Edward O'Callaghan has uploaded a new patch set (#10) to the change originally created by Nikolai Artemiev. ( https://review.coreboot.org/c/flashrom/+/70517 ) Change subject: flashrom: Check for flash access restrictions in erase path ...................................................................... flashrom: Check for flash access restrictions in erase path Skip unwritable regions if FLASHROM_FLAG_SKIP_UNWRITABLE_REGIONS is true. If the flag is false, erase operations that include an unwritable region will not erase anything and return an error. BUG=b:260440773 BRANCH=none TEST=flashrom -E on dedede (JSL) Change-Id: If027a96a024782c7707c6d38680709a1a117f3ef CoAuthored-by: Edward O'Callaghan <quasisec(a)google.com> Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashrom.c 1 file changed, 51 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/70517/10 -- To view, visit https://review.coreboot.org/c/flashrom/+/70517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: If027a96a024782c7707c6d38680709a1a117f3ef Gerrit-Change-Number: 70517 Gerrit-PatchSet: 10 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in flashrom[master]: Add initial CH347T SPI programmer
by qianfan (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Nicholas Chin, Angel Pons. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70529 to look at the new patch set (#5). Change subject: Add initial CH347T SPI programmer ...................................................................... Add initial CH347T SPI programmer Tested with CH347T-EVK flash chip W25Q16.V. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> Change-Id: I6da5e308af76693e60308c8165349128e517e09a --- M Makefile A ch347t_spi.c M include/programmer.h M programmer_table.c 4 files changed, 496 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/70529/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/70529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da5e308af76693e60308c8165349128e517e09a Gerrit-Change-Number: 70529 Gerrit-PatchSet: 5 Gerrit-Owner: qianfan <qianfanguijin(a)163.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in flashrom[master]: Add initial CH347T SPI programmer
by qianfan (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Nicholas Chin, Angel Pons. Hello build bot (Jenkins), Thomas Heijligen, Angel Pons, Nicholas Chin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/70529 to look at the new patch set (#4). Change subject: Add initial CH347T SPI programmer ...................................................................... Add initial CH347T SPI programmer Tested with CH347T-EVK flash chip W25Q16.V. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> Change-Id: I6da5e308af76693e60308c8165349128e517e09a --- M Makefile A ch347t_spi.c M include/programmer.h M programmer_table.c 4 files changed, 496 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/70529/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/70529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I6da5e308af76693e60308c8165349128e517e09a Gerrit-Change-Number: 70529 Gerrit-PatchSet: 4 Gerrit-Owner: qianfan <qianfanguijin(a)163.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in flashrom[master]: spi: Make 'default_spi_write_aai' the default unless defined
by Felix Singer (Code Review) 21 Dec '22

21 Dec '22

Felix Singer has submitted this change. ( https://review.coreboot.org/c/flashrom/+/67479 ) Change subject: spi: Make 'default_spi_write_aai' the default unless defined ...................................................................... spi: Make 'default_spi_write_aai' the default unless defined A NULL func pointer is necessary and sufficient for the condition `NULL func pointer => default_spi_write_aai' as to not need this explicit specification of 'default'. Therefore Drop the explicit need to specify the 'default_spi_write_aai' callback function pointer in the spi_master struct. This is a reasonable default for every other driver in the tree with only a few exceptions. This simplifies the code and driver development. Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/67479 Reviewed-by: Peter Marheine <pmarheine(a)chromium.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M bitbang_spi.c M buspirate_spi.c M ch341a_spi.c M digilent_spi.c M dummyflasher.c M ft2232_spi.c M ichspi.c M jlink_spi.c M linux_spi.c M mediatek_i2c_spi.c M mstarddc_spi.c M ni845x_spi.c M pickit2_spi.c M raiden_debug_spi.c M sb600spi.c M serprog.c M spi.c M stlinkv3_spi.c M usbblaster_spi.c 19 files changed, 28 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Peter Marheine: Looks good to me, but someone else must approve Anastasia Klimchuk: Looks good to me, approved diff --git a/bitbang_spi.c b/bitbang_spi.c index fadca70..7919e45 100644 --- a/bitbang_spi.c +++ b/bitbang_spi.c @@ -146,7 +146,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = bitbang_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/buspirate_spi.c b/buspirate_spi.c index dbaac4e..a40fb70 100644 --- a/buspirate_spi.c +++ b/buspirate_spi.c @@ -181,7 +181,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = buspirate_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/ch341a_spi.c b/ch341a_spi.c index fe18d13..75eaf86 100644 --- a/ch341a_spi.c +++ b/ch341a_spi.c @@ -416,7 +416,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = ch341a_spi_shutdown, .probe_opcode = default_spi_probe_opcode, .delay = ch341a_spi_delay, diff --git a/digilent_spi.c b/digilent_spi.c index 6575cbf..55cb6ec 100644 --- a/digilent_spi.c +++ b/digilent_spi.c @@ -336,7 +336,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = digilent_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/dummyflasher.c b/dummyflasher.c index e5a9c12..1960e92 100644 --- a/dummyflasher.c +++ b/dummyflasher.c @@ -929,7 +929,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = dummy_spi_write_256, - .write_aai = default_spi_write_aai, .probe_opcode = dummy_spi_probe_opcode, }; diff --git a/ft2232_spi.c b/ft2232_spi.c index aec21bc..dfec1a0 100644 --- a/ft2232_spi.c +++ b/ft2232_spi.c @@ -299,7 +299,6 @@ .multicommand = ft2232_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = ft2232_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/ichspi.c b/ichspi.c index 7b23b42..1522d2b 100644 --- a/ichspi.c +++ b/ichspi.c @@ -1947,7 +1947,6 @@ .unmap_flash_region = physunmap, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, }; static const struct spi_master spi_master_ich9 = { @@ -1959,7 +1958,6 @@ .unmap_flash_region = physunmap, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .probe_opcode = ich_spi_probe_opcode, }; @@ -2383,7 +2381,6 @@ .unmap_flash_region = physunmap, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .probe_opcode = ich_spi_probe_opcode, }; diff --git a/jlink_spi.c b/jlink_spi.c index 63d15b8..ad2ca78 100644 --- a/jlink_spi.c +++ b/jlink_spi.c @@ -187,7 +187,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .features = SPI_MASTER_4BA, .shutdown = jlink_spi_shutdown, .probe_opcode = default_spi_probe_opcode, diff --git a/linux_spi.c b/linux_spi.c index ee02304..d65b3e8 100644 --- a/linux_spi.c +++ b/linux_spi.c @@ -119,7 +119,6 @@ .multicommand = default_spi_send_multicommand, .read = linux_spi_read, .write_256 = linux_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = linux_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/mediatek_i2c_spi.c b/mediatek_i2c_spi.c index 3aa9dd9..c15df05 100644 --- a/mediatek_i2c_spi.c +++ b/mediatek_i2c_spi.c @@ -459,7 +459,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = mediatek_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/mstarddc_spi.c b/mstarddc_spi.c index 0c11717..bd65281 100644 --- a/mstarddc_spi.c +++ b/mstarddc_spi.c @@ -145,7 +145,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = mstarddc_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/ni845x_spi.c b/ni845x_spi.c index 2750334..fd5057d 100644 --- a/ni845x_spi.c +++ b/ni845x_spi.c @@ -535,7 +535,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = ni845x_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/pickit2_spi.c b/pickit2_spi.c index e8c80af..86c5403 100644 --- a/pickit2_spi.c +++ b/pickit2_spi.c @@ -383,7 +383,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = pickit2_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/raiden_debug_spi.c b/raiden_debug_spi.c index 8260abd..d1a09d7 100644 --- a/raiden_debug_spi.c +++ b/raiden_debug_spi.c @@ -1323,7 +1323,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = raiden_debug_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/sb600spi.c b/sb600spi.c index 8c018a3..5b9ac45 100644 --- a/sb600spi.c +++ b/sb600spi.c @@ -604,7 +604,6 @@ .unmap_flash_region = physunmap, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; @@ -618,7 +617,6 @@ .unmap_flash_region = physunmap, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; @@ -632,7 +630,6 @@ .unmap_flash_region = physunmap, .read = promontory_read_memmapped, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = sb600spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/serprog.c b/serprog.c index 84dfd23..4e131e5 100644 --- a/serprog.c +++ b/serprog.c @@ -464,7 +464,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .probe_opcode = default_spi_probe_opcode, .delay = serprog_delay, }; diff --git a/spi.c b/spi.c index e708ba9..6c2c4c4 100644 --- a/spi.c +++ b/spi.c @@ -131,7 +131,9 @@ int spi_aai_write(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len) { - return flash->mst->spi.write_aai(flash, buf, start, len); + if (flash->mst->spi.write_aai) + return flash->mst->spi.write_aai(flash, buf, start, len); + return default_spi_write_aai(flash, buf, start, len); } bool default_spi_probe_opcode(const struct flashctx *flash, uint8_t opcode) @@ -150,7 +152,7 @@ } } - if (!mst->write_aai || !mst->write_256 || !mst->read || !mst->command || + if (!mst->write_256 || !mst->read || !mst->command || !mst->multicommand || !mst->probe_opcode || ((mst->command == default_spi_send_command) && (mst->multicommand == default_spi_send_multicommand))) { diff --git a/stlinkv3_spi.c b/stlinkv3_spi.c index 1d5763b..16a66b4 100644 --- a/stlinkv3_spi.c +++ b/stlinkv3_spi.c @@ -469,7 +469,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = stlinkv3_spi_shutdown, .probe_opcode = default_spi_probe_opcode, }; diff --git a/usbblaster_spi.c b/usbblaster_spi.c index 5e2c020..75d5be7 100644 --- a/usbblaster_spi.c +++ b/usbblaster_spi.c @@ -171,7 +171,6 @@ .multicommand = default_spi_send_multicommand, .read = default_spi_read, .write_256 = default_spi_write_256, - .write_aai = default_spi_write_aai, .shutdown = usbblaster_shutdown, .probe_opcode = default_spi_probe_opcode, }; -- To view, visit https://review.coreboot.org/c/flashrom/+/67479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Gerrit-Change-Number: 67479 Gerrit-PatchSet: 7 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in flashrom[master]: spi: Make 'default_spi_write_aai' the default unless defined
by Felix Singer (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Thomas Heijligen, Edward O'Callaghan. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/67479 ) Change subject: spi: Make 'default_spi_write_aai' the default unless defined ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS1: > Addressed the first part in the commit message by making clear the mathematical constraint here in p […] I think the patch is fine as it is now. A rename might be good, but I agree that should be done in a separate patch. I remember we didn't do the rename in others. -- To view, visit https://review.coreboot.org/c/flashrom/+/67479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I7f14aaea0edcf0c08cea0e9cd27d58152707fb2a Gerrit-Change-Number: 67479 Gerrit-PatchSet: 6 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Wed, 21 Dec 2022 04:44:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Thomas Heijligen <src(a)posteo.de> Comment-In-Reply-To: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: comment

1 0

[M] Change in flashrom[master]: cli_classic.c: Allow ctrl of behaviour with WO and RO regions
by Felix Singer (Code Review) 21 Dec '22

21 Dec '22

Attention is currently required from: Edward O'Callaghan, Angel Pons, Nikolai Artemiev. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/70895 ) Change subject: cli_classic.c: Allow ctrl of behaviour with WO and RO regions ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/70895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iff753b748765410ea38b845613c361db7ad16a61 Gerrit-Change-Number: 70895 Gerrit-PatchSet: 5 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Wed, 21 Dec 2022 04:30:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

flashrom-gerrit