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[M] Change in flashrom[master]: writeprotect,ichspi,spi25: handle register access constraints
by Nikolai Artemiev (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Subrata Banik, Nikolai Artemiev. Hello build bot (Jenkins), Subrata Banik, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69129 to look at the new patch set (#5). Change subject: writeprotect,ichspi,spi25: handle register access constraints ...................................................................... writeprotect,ichspi,spi25: handle register access constraints Make the spi25 register read/write functions return SPI_INVALID_OPCODE if the programmer blocks the read/write opcode for the register. Likewise, make ichspi read/write register functions return SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd. Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to read/write SR1, which should always be supported. BUG=b:253715389,b:253713774 BRANCH=none TEST=builds Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c M spi25_statusreg.c M writeprotect.c 3 files changed, 75 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/69129/5 -- To view, visit https://review.coreboot.org/c/flashrom/+/69129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Gerrit-Change-Number: 69129 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: ichspi.c: read chip ID and use it to identify chip
by Nikolai Artemiev (Code Review) 04 Nov '22

04 Nov '22

Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/69195 ) Change subject: ichspi.c: read chip ID and use it to identify chip ...................................................................... ichspi.c: read chip ID and use it to identify chip BUG=b:253715389,b:253713774 BRANCH=none TEST=builds Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/95/69195/1 diff --git a/ichspi.c b/ichspi.c index 6d3535c..22fe7cd 100644 --- a/ichspi.c +++ b/ichspi.c @@ -132,6 +132,7 @@ #define HSFC_CYCLE_READ HSFC_FCYCLE_MASK(0) #define HSFC_CYCLE_WRITE HSFC_FCYCLE_MASK(2) #define HSFC_CYCLE_BLOCK_ERASE HSFC_FCYCLE_MASK(3) +#define HSFC_CYCLE_RDID HSFC_FCYCLE_MASK(6) #define HSFC_CYCLE_WR_STATUS HSFC_FCYCLE_MASK(7) #define HSFC_CYCLE_RD_STATUS HSFC_FCYCLE_MASK(8) /* 3-7: reserved */ @@ -1388,6 +1389,19 @@ return ich_hwseq_wait_for_cycle_complete(len, ich_gen, addr_mask); } +/* Given RDID info, return pointer to entry in flashchips[] */ +static const struct flashchip *flash_id_to_entry(uint32_t mfg_id, uint32_t model_id) +{ + const struct flashchip *chip; + + for (chip = &flashchips[0]; chip->vendor; chip++) { + if ((chip->manufacture_id == mfg_id) && (chip->model_id == model_id)) + return chip; + } + + return NULL; +} + static int ich_hwseq_read_status(const struct flashctx *flash, enum flash_reg reg, uint8_t *value) { const int len = 1; @@ -1431,6 +1445,53 @@ return 0; } +static int ich_hwseq_get_flash_id(struct flashctx *flash, enum ich_chipset ich_gen) +{ + uint32_t data, mfg_id, model_id; + const struct flashchip *entry; + const int len = sizeof(data); + const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); + + if (ich_exec_sync_hwseq_xfer(HSFC_CYCLE_RDID, 0, len, ich_generation, + hwseq_data->addr_mask)) { + msg_perr("Timed out waiting for RDID to complete.\n"); + return 0; + } + + /* + * Data will appear in reverse order: + * Byte 0: Manufacturer ID + * Byte 1: Model ID (MSB) + * Byte 2: Model ID (LSB) + */ + ich_read_data((uint8_t *)&data, len, ICH9_REG_FDATA0); + mfg_id = data & 0xff; + model_id = (data & 0xff00) | ((data >> 16) & 0xff); + + entry = flash_id_to_entry(mfg_id, model_id); + if (entry == NULL) { + msg_perr("Unable to identify chip, mfg_id: 0x%02x, " + "model_id: 0x%02x\n", mfg_id, model_id); + return 0; + } else { + msg_pdbg("Chip identified: %s\n", entry->name); + /* Update informational flash chip entries only */ + flash->chip->vendor = entry->vendor; + flash->chip->name = entry->name; + flash->chip->manufacture_id = entry->manufacture_id; + flash->chip->model_id = entry->model_id; + /* total_size read from flash descriptor */ + flash->chip->page_size = entry->page_size; + flash->chip->feature_bits = entry->feature_bits; + flash->chip->tested = entry->tested; + /* support writeprotect. */ + flash->chip->reg_bits = entry->reg_bits; + flash->chip->decode_range = entry->decode_range; + } + + return 1; +} + static int ich_hwseq_probe(struct flashctx *flash) { uint32_t total_size, boundary; @@ -1438,6 +1499,11 @@ struct block_eraser *eraser; const struct hwseq_data *hwseq_data = get_hwseq_data_from_context(flash); + if (ich_hwseq_get_flash_id(flash, ich_generation) != 1) { + msg_perr("Unable to read flash chip ID\n"); + return 0; + } + total_size = hwseq_data->size_comp0 + hwseq_data->size_comp1; msg_cdbg("Hardware sequencing reports %d attached SPI flash chip", (hwseq_data->size_comp1 != 0) ? 2 : 1); -- To view, visit https://review.coreboot.org/c/flashrom/+/69195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia408e1e45dc6f53c0934afd6558e301abfa48ee6 Gerrit-Change-Number: 69195 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newchange

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[M] Change in flashrom[master]: writeprotect,ichspi,spi25: handle register access constraints
by Edward O'Callaghan (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Subrata Banik, Nikolai Artemiev. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69129 ) Change subject: writeprotect,ichspi,spi25: handle register access constraints ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/69129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Gerrit-Change-Number: 69129 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 03:26:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: writeprotect,ichspi,spi25: handle register access constraints
by Nikolai Artemiev (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Subrata Banik, Edward O'Callaghan. Hello build bot (Jenkins), Subrata Banik, Edward O'Callaghan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69129 to look at the new patch set (#3). Change subject: writeprotect,ichspi,spi25: handle register access constraints ...................................................................... writeprotect,ichspi,spi25: handle register access constraints Make the spi25 register read/write functions return SPI_INVALID_OPCODE if the programmer blocks the read/write opcode for the register. Likewise, make ichspi read/write register functions return SPI_INVALID_OPCODE for registers >SR1 as they cannot be accessd. Make writeprotect ignore SPI_INVALID_OPCODE unless it is trying to read/write SR1, which should always be supported. BUG=b:253715389,b:253713774 BRANCH=none TEST=builds Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M ichspi.c M spi25_statusreg.c M writeprotect.c 3 files changed, 75 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/29/69129/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/69129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2145749dcc51f4556550650dab5aa1049f879c45 Gerrit-Change-Number: 69129 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[1.3.x]: sb600spi.c: Drop "Promontory" support
by Edward O'Callaghan (Code Review) 04 Nov '22

04 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen, Angel Pons, Anastasia Klimchuk. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68824 ) Change subject: sb600spi.c: Drop "Promontory" support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Gerrit-Change-Number: 68824 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Nov 2022 03:09:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: writeprotect_ranges.c: add more range functions
by Anastasia Klimchuk (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nico Huber, Maciej Pijanowski, Angel Pons, Nikolai Artemiev, Sergii Dmytruk. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/66212 ) Change subject: writeprotect_ranges.c: add more range functions ...................................................................... Patch Set 8: (1 comment) Patchset: PS3: > Thanks for committing those. […] Okay, I am resolving this comment thread, seems like all done here. I will look into the discussion you mentioned, will see how we can move it forward -- To view, visit https://review.coreboot.org/c/flashrom/+/66212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ied7b27be2ee2426af8f473432e2b01a290de2365 Gerrit-Change-Number: 66212 Gerrit-PatchSet: 8 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 01:39:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Anastasia Klimchuk (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nikolai Artemiev. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69130 ) Change subject: tests: ensure chip erase operation is executed ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File include/flash.h: https://review.coreboot.org/c/flashrom/+/69130/comment/83e009de_c566bf8a PS1, Line 159: #define UNERASED_VALUE(flash) > It's a useful counterpart to `ERASED_VALUE()` and it might be helpful for erase optimization code et […] The thoughts I had: we have ERASED_VALUE which is one value (for a given chip), but technically unerased value is any other value which is not ERASED_VALUE. Like for a real chip, there could be any data written. There is no such operation as "unerase chip". For unit tests, yes it makes sense to create a mock "unerased chip memory" with just one and the same "unerased value". If everyone else agrees, I am fine to have the macro here. -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:29:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nikolai Artemiev <nartemiev(a)google.com> Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Nikolai Artemiev (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Anastasia Klimchuk. Nikolai Artemiev has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/69130 ) Change subject: tests: ensure chip erase operation is executed ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/flashrom/+/69130/comment/977d339b_1fa0484f PS1, Line 18: (hopefully) > "and is expected to fail" I have rephrased this sentence a bit now. https://review.coreboot.org/c/flashrom/+/69130/comment/7b6f389a_3162107a PS1, Line 18: exectued > exectued -> executed (typo) Done File include/flash.h: https://review.coreboot.org/c/flashrom/+/69130/comment/545a7087_b748f374 PS1, Line 159: #define UNERASED_VALUE(flash) > Will this ever be needed outside of tests? […] It's a useful counterpart to `ERASED_VALUE()` and it might be helpful for erase optimization code etc, so I think it makes sense to leave them both here. -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[1.3.x]: sb600spi.c: Drop "Promontory" support
by Swift Geek (Sebastian Grzywna) (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nico Huber, Thomas Heijligen, Edward O'Callaghan, Angel Pons, Anastasia Klimchuk. Swift Geek (Sebastian Grzywna) has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/68824 ) Change subject: sb600spi.c: Drop "Promontory" support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/68824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: 1.3.x Gerrit-Change-Id: I1457946dce68321b496d9ffa40a0c5ab46455f72 Gerrit-Change-Number: 68824 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Swift Geek (Sebastian Grzywna) <swiftgeek(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Comment-Date: Fri, 04 Nov 2022 00:19:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[master]: tests: ensure chip erase operation is executed
by Nikolai Artemiev (Code Review) 03 Nov '22

03 Nov '22

Attention is currently required from: Nikolai Artemiev. Hello build bot (Jenkins), Edward O'Callaghan, Angel Pons, Anastasia Klimchuk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/69130 to look at the new patch set (#3). Change subject: tests: ensure chip erase operation is executed ...................................................................... tests: ensure chip erase operation is executed The `full_chip_erase_with_wp_dummyflasher_test_success` test case checks that erasing a write-protected region of a dummyflasher chip fails. However erase optimization may cause the erase operation to be skipped if the flash contents are already erased, so the erase operation appears to succeed and the test case fails. Writing a non-erased value to the chip ensures that an erase operation will be executed and write protection will be properly tested. BUG=b:237620197 BRANCH=none TEST=ninja test Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Signed-off-by: Nikolai Artemiev <nartemiev(a)google.com> --- M include/flash.h M tests/chip_wp.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/69130/3 -- To view, visit https://review.coreboot.org/c/flashrom/+/69130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia00444dcd2ad96c64832a13201efbd064cd7302d Gerrit-Change-Number: 69130 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-MessageType: newpatchset

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