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[S] Change in flashrom[master]: flashrom.c: Add switch for legacy impl of erasure path
by Anastasia Klimchuk (Code Review) 13 Feb '23

13 Feb '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/71119 ) Change subject: flashrom.c: Add switch for legacy impl of erasure path ...................................................................... flashrom.c: Add switch for legacy impl of erasure path As part of a GSoC project to optimise the erasure path in flashrom a completely different algorithm is used to perform erasure. Therefore we need a mechanism to have the two implementations side by side to allow for A/B testing and easy reverts should issue arise. Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/71119 Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Thomas Heijligen <src(a)posteo.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M flashrom.c 1 file changed, 40 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Thomas Heijligen: Looks good to me, approved Edward O'Callaghan: Looks good to me, approved Anastasia Klimchuk: Looks good to me, approved diff --git a/flashrom.c b/flashrom.c index f26bb47..1790ad9 100644 --- a/flashrom.c +++ b/flashrom.c @@ -34,6 +34,8 @@ #include "hwaccess_physmap.h" #include "chipdrivers.h" +static bool use_legacy_erase_path = true; + const char flashrom_version[] = FLASHROM_VERSION; static const struct programmer_entry *programmer = NULL; @@ -1528,13 +1530,20 @@ * @return 0 on success, * 1 if all available erase functions failed. */ -static int erase_by_layout(struct flashctx *const flashctx) +static int erase_by_layout_legacy(struct flashctx *const flashctx) { struct walk_info info = { 0 }; bool all_skipped = true; return walk_by_layout(flashctx, &info, &erase_block, &all_skipped); } +static int erase_by_layout(struct flashctx *const flashctx) +{ + if (use_legacy_erase_path) + return erase_by_layout_legacy(flashctx); + return 1; /* unimplemented. */ +} + static int read_erase_write_block(struct flashctx *const flashctx, const struct walk_info *const info, const erasefn_t erasefn, bool *all_skipped) @@ -1643,7 +1652,7 @@ * @return 0 on success, * 1 if anything has gone wrong. */ -static int write_by_layout(struct flashctx *const flashctx, +static int write_by_layout_legacy(struct flashctx *const flashctx, void *const curcontents, const void *const newcontents, bool *all_skipped) { @@ -1653,6 +1662,15 @@ return walk_by_layout(flashctx, &info, read_erase_write_block, all_skipped); } +static int write_by_layout(struct flashctx *const flashctx, + uint8_t *const curcontents, const uint8_t *const newcontents, + bool *all_skipped) +{ + if (use_legacy_erase_path) + return write_by_layout_legacy(flashctx, curcontents, newcontents, all_skipped); + return 1; /* unimplemented. */ +} + /** * @brief Compares the included layout regions with content from a buffer. * -- To view, visit https://review.coreboot.org/c/flashrom/+/71119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ib5660db0067c1c799dcb5c8e83b4a4826b236442 Gerrit-Change-Number: 71119 Gerrit-PatchSet: 15 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[master]: flashrom.c: Trivial code style fix
by Edward O'Callaghan (Code Review) 13 Feb '23

13 Feb '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72968 ) Change subject: flashrom.c: Trivial code style fix ...................................................................... flashrom.c: Trivial code style fix Change-Id: Iacdb62067a8d22261d4eabe73ad96168eb11417c Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M flashrom.c 1 file changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/72968/1 diff --git a/flashrom.c b/flashrom.c index f26bb47..9a0cb4c 100644 --- a/flashrom.c +++ b/flashrom.c @@ -1279,8 +1279,7 @@ ret = 1; } } - if(curr_eraseblock_count > prev_eraseblock_count) - { + if (curr_eraseblock_count > prev_eraseblock_count) { msg_gerr("ERROR: Flash chip %s erase function %i is not " "in order. Please report a bug at flashrom(a)flashrom.org\n", chip->name, k); -- To view, visit https://review.coreboot.org/c/flashrom/+/72968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Iacdb62067a8d22261d4eabe73ad96168eb11417c Gerrit-Change-Number: 72968 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in flashrom[master]: cli_classic.c: Drop spurious cast
by Sam McNally (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Edward O'Callaghan. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72966 ) Change subject: cli_classic.c: Drop spurious cast ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Gerrit-Change-Number: 72966 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Mon, 13 Feb 2023 02:35:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in flashrom[master]: Add support for AMD Ryzen flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Arthur Heymans, Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72058 ) Change subject: Add support for AMD Ryzen flashing ...................................................................... Patch Set 3: (1 comment) Commit Message: PS1: > Please remove the extra newlines in the commit body (everything after the commit summary and before […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/72058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Gerrit-Change-Number: 72058 Gerrit-PatchSet: 3 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 02:27:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[L] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Thomas Heijligen, Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72057 ) Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Patch Set 3: (1 comment) Commit Message: PS1: > Please remove the extra newlines in the commit body (everything after the commit summary and before […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 3 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 02:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id.
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: Nicholas Chin. ChrisEric1 CECL has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/72056 ) Change subject: Add missing Intel B460 flash chip id. ...................................................................... Patch Set 3: (1 comment) Commit Message: PS1: > Please remove the extra newlines in the commit body (everything after the commit summary and before […] Done -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 3 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Feb 2023 02:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in flashrom[master]: cli_classic.c: Drop spurious cast
by Edward O'Callaghan (Code Review) 13 Feb '23

13 Feb '23

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/72966 ) Change subject: cli_classic.c: Drop spurious cast ...................................................................... cli_classic.c: Drop spurious cast This cast should not be required. Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Signed-off-by: Edward O'Callaghan <quasisec(a)google.com> --- M cli_classic.c 1 file changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/66/72966/1 diff --git a/cli_classic.c b/cli_classic.c index c72836f..da68919 100644 --- a/cli_classic.c +++ b/cli_classic.c @@ -662,8 +662,7 @@ * chip when a flash device gets opened with fd 1 or 2. */ if (check_file(stdout) && check_file(stderr)) { - flashrom_set_log_callback( - (flashrom_log_callback *)&flashrom_print_cb); + flashrom_set_log_callback(&flashrom_print_cb); } print_version(); -- To view, visit https://review.coreboot.org/c/flashrom/+/72966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ia3a658dd6f4986eb6da84a11bce66f53e1571469 Gerrit-Change-Number: 72966 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in flashrom[master]: Add support for VIA VL805 USB 3 XHCI flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Thomas Heijligen. Hello build bot (Jenkins), Thomas Heijligen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72057 to look at the new patch set (#2). Change subject: Add support for VIA VL805 USB 3 XHCI flashing ...................................................................... Add support for VIA VL805 USB 3 XHCI flashing It works fine for me on my Raspberry Pi 4 Model B. Was able read read, erase, write, verify. Only thing is the WP with the W25X10 gives a untested warning. And I changed W25X10 to RDID4 since it wouldn't work otherwise. Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M Makefile M flashchips.c M flashrom.8.tmpl M include/programmer.h M programmer_table.c A vl805.c 6 files changed, 259 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/72057/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I71435afcacdf97e14d627e35bce3d29de9657f38 Gerrit-Change-Number: 72057 Gerrit-PatchSet: 2 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[master]: Add missing Intel B460 flash chip id.
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72056 to look at the new patch set (#2). Change subject: Add missing Intel B460 flash chip id. ...................................................................... Add missing Intel B460 flash chip id. Note that while I can read the chip, on my Lenovo Legion T5 28IMB05, cannot write to the flash chip with any tools except upgrading with vendor tool, no downgrades are allowed, due to the fact of SMM, even if I did manage to flash the BIOS chip somehow, would still face bootguard since this machine has bootguard. But if I read the chip, and verify my read bin file, it works fine, until changing the SMBIOS, which is in the vendor BIOS update package. Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M chipset_enable.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/56/72056/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Id8fcb59d5dbafea3e79c4e3ad75484bbd163feca Gerrit-Change-Number: 72056 Gerrit-PatchSet: 2 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in flashrom[master]: Add support for AMD Ryzen flashing
by ChrisEric1 CECL (Code Review) 13 Feb '23

13 Feb '23

Attention is currently required from: ChrisEric1 CECL, Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/72058 to look at the new patch set (#2). Change subject: Add support for AMD Ryzen flashing ...................................................................... Add support for AMD Ryzen flashing Tested AMD Ryzen Support on HP Pavilion 590-p0077c, I am able to flash using F.15 or older, but I can downgrade if a newer Firmware is installed using afuwinx64 which is a vendor tool This is due to flashrom SPI lockdown on newer firmwares by HP. It seems HP UEFI Diags uses AFU Flash embedded in. It also comes with a AMD Ryzen 3 2200G with 16MB, so it may not work with chips more that 16MB, it is currently untested by me, since this is the only AMD PC I own. Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Signed-off-by: Christopher Lentocha <christopherericlentocha(a)gmail.com> --- M chipset_enable.c M flashchips.c M include/flashchips.h M include/programmer.h M sb600spi.c M spi25.c 6 files changed, 127 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/58/72058/2 -- To view, visit https://review.coreboot.org/c/flashrom/+/72058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: Ife51f7dec31b51a7416e417112b0eedb21fae6a0 Gerrit-Change-Number: 72058 Gerrit-PatchSet: 2 Gerrit-Owner: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: ChrisEric1 CECL <christopherericlentocha(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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