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Change subject: flashchips: Test MXIC MX25U25643G wp
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/flashrom/+/78142/comment/47607b27_17845925 :
PS2, Line 7: Test MXIC MX25U25643G wp
replace with:
flashchips: Add write-protect support for MXIC MX25U25643G
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Change subject: flashchips: Test MXIC MX25U25643G wp
......................................................................
Patch Set 2:
(2 comments)
Patchset:
PS2:
Thank you for the patch! I have one comment, please see below.
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/78142/comment/c1e4167c_14bd3b74 :
PS2, Line 10308: STATUS2
Should this be CONFIG ? TB bit is defined in configuration register (Table 8).
I hope I am not mistaken.
Commit message says you tested WP, could you maybe give a detailed list of WP commands that you tested?
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Change subject: doc: Make Time of Meeting more consistent
......................................................................
Patch Set 1: Code-Review+2
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Change subject: doc: Make Time of Meeting more consistent
......................................................................
doc: Make Time of Meeting more consistent
Change-Id: I8b37d2913750946c71908e94fcd3041766f1b59d
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
M doc/contact.rst
1 file changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/88/78188/1
diff --git a/doc/contact.rst b/doc/contact.rst
index 5bcac3f..57a9390 100644
--- a/doc/contact.rst
+++ b/doc/contact.rst
@@ -111,19 +111,19 @@
also known as
- | Wednesday 13.00-14.00 Pacific Standard Time UTC-8
- | Wednesday 22.00-23.00 Central European Time UTC+1
- | Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11
+ | Wednesday 13:00-14:00 Pacific Standard Time UTC-8
+ | Wednesday 22:00-23:00 Central European Time UTC+1
+ | Thursday 8:00-9:00 Australian Eastern Daylight Time UTC+11
Between April and September (inclusive)
- **Thursday 6.00-7.00am UTC+0**
+ **Thursday 6:00-7:00 UTC+0**
also known as
- | Wednesday 11pm-midnight Pacific Daylight Time UTC-7
- | Thursday 8.00-9.00am Central European Summer Time UTC+2
- | Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10
+ | Wednesday 23:00-midnight Pacific Daylight Time UTC-7
+ | Thursday 8:00-9:00 Central European Summer Time UTC+2
+ | Thursday 16:00-17:00 Australian Eastern Standard Time UTC+10
The last week of March and 4 weeks of October there are no meetings
This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated.
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Change subject: ichspi: Add support for C740 PCH
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I only tested a back-ported patch against flashrom v1.21 using the linux_mtd driver.
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Hello Patrick Rudolph,
I'd like you to do a code review.
Please visit
https://review.coreboot.org/c/flashrom/+/78186?usp=email
to review the following change.
Change subject: ichspi: Add support for C740 PCH
......................................................................
ichspi: Add support for C740 PCH
Add Intel Emmitsburg detection support.
Change-Id: I80eebc0fcc14de9df823aceaee77870ad136f94a
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M chipset_enable.c
M ich_descriptors.c
M ichspi.c
M include/programmer.h
4 files changed, 25 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/86/78186/1
diff --git a/chipset_enable.c b/chipset_enable.c
index 3846ecf..8da0e6d 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -601,6 +601,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -712,6 +713,7 @@
break;
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_600_SERIES_ALDER_POINT:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_METEOR_LAKE:
boot_straps = boot_straps_pch500;
break;
diff --git a/ich_descriptors.c b/ich_descriptors.c
index a2a99bd..548e6ab 100644
--- a/ich_descriptors.c
+++ b/ich_descriptors.c
@@ -44,6 +44,7 @@
case CHIPSET_GEMINI_LAKE:
return 6;
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -75,6 +76,7 @@
{
switch (cs) {
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_APOLLO_LAKE:
case CHIPSET_600_SERIES_ALDER_POINT:
case CHIPSET_METEOR_LAKE:
@@ -117,9 +119,9 @@
"5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
- "C620 series Lewisburg", "300 series Cannon Point", "400 series Comet Point",
- "500 series Tiger Point", "600 series Alder Point", "Meteor Lake",
- "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake",
+ "C620 series Lewisburg", "C740 series Emmitsburg", "300 series Cannon Point",
+ "400 series Comet Point", "500 series Tiger Point", "600 series Alder Point",
+ "Meteor Lake", "Apollo Lake", "Gemini Lake", "Jasper Lake", "Elkhart Lake",
};
if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
cs = 0;
@@ -211,6 +213,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -304,6 +307,7 @@
return freq_str[0][value];
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_JASPER_LAKE:
@@ -357,6 +361,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -489,6 +494,7 @@
cs == CHIPSET_400_SERIES_COMET_POINT ||
cs == CHIPSET_500_SERIES_TIGER_POINT ||
cs == CHIPSET_600_SERIES_ALDER_POINT ||
+ cs == CHIPSET_C740_SERIES_EMMITSBURG ||
cs == CHIPSET_JASPER_LAKE || cs == CHIPSET_METEOR_LAKE) {
const char *const master_names[] = {
"BIOS", "ME", "GbE", "unknown", "EC",
@@ -1023,6 +1029,8 @@
}
if (content->ISL <= 80)
return CHIPSET_C620_SERIES_LEWISBURG;
+ if (content->ISL == 0x50)
+ return CHIPSET_C740_SERIES_EMMITSBURG;
warn_peculiar_desc("Ibex Peak");
return CHIPSET_5_SERIES_IBEX_PEAK;
} else if (upper->MDTBA == 0x00) {
@@ -1095,6 +1103,7 @@
break;
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_APOLLO_LAKE:
if (component->modes.freq_read != 6) {
msg_pwarn("\nThe flash descriptor looks like a Skylake/Sunrise Point descriptor.\n"
@@ -1242,6 +1251,7 @@
case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -1287,6 +1297,7 @@
switch (cs) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
diff --git a/ichspi.c b/ichspi.c
index 2e38ff1..d2e0322 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -457,6 +457,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -470,6 +471,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -492,6 +494,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2050,6 +2053,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2087,6 +2091,7 @@
*num_freg = 10;
break;
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
*num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
break;
case CHIPSET_300_SERIES_CANNON_POINT:
@@ -2150,6 +2155,7 @@
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2230,6 +2236,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
@@ -2269,6 +2276,7 @@
case CHIPSET_ICH8:
case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG:
+ case CHIPSET_C740_SERIES_EMMITSBURG:
case CHIPSET_300_SERIES_CANNON_POINT:
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
diff --git a/include/programmer.h b/include/programmer.h
index 562f58a..15df0d4 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -354,6 +354,7 @@
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
+ CHIPSET_C740_SERIES_EMMITSBURG,
CHIPSET_300_SERIES_CANNON_POINT,
CHIPSET_400_SERIES_COMET_POINT,
CHIPSET_500_SERIES_TIGER_POINT,
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Change subject: doc: Convert release notes for v1.3
......................................................................
Patch Set 2:
(2 comments)
File doc/release_notes/v_1_3.rst:
https://review.coreboot.org/c/flashrom/+/78116/comment/4bd1e17a_b54b3f99 :
PS1, Line 106: :code:`libftdi1, libjaylink, libusb1, libpci`
> ``` […]
Done.
I tried to make a shortcut, but you noticed :)
https://review.coreboot.org/c/flashrom/+/78116/comment/7ee3d403_d8b38f91 :
PS1, Line 108: :code:`compiler, hwlibs, features`
> ``` […]
Done
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Attention is currently required from: Alexander Goncharov, Anastasia Klimchuk, Thomas Heijligen.
Hello Alexander Goncharov, Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78116?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+2 by Alexander Goncharov, Verified+1 by build bot (Jenkins)
Change subject: doc: Convert release notes for v1.3
......................................................................
doc: Convert release notes for v1.3
Change-Id: I5b66a957249c3025715eff2b00f1be9eb0d36096
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
---
M doc/index.rst
A doc/release_notes/index.rst
A doc/release_notes/v_1_3.rst
3 files changed, 222 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/16/78116/2
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