Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, Thomas Heijligen.
Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, Thomas Heijligen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/78142?usp=email
to look at the new patch set (#4).
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
The MX25U25643G has been tested by ch341a programmer : read, write, erase and wp.
The MX25U25643G has been tested by ch341a programmer : read, write,
erase and wp.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp…
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou(a)mxic.com.cn>
---
M flashchips.c
1 file changed, 58 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/78142/4
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Attention is currently required from: Nikolai Artemiev, Stefan Reinauer, rogeryou.
Hello Anastasia Klimchuk, Nikolai Artemiev, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: flashchips: Add write-protect support for MXIC MX25U25643G
......................................................................
flashchips: Add write-protect support for MXIC MX25U25643G
The MX25U25643G has a WPSEL bit in the security register, but the MX25U25635F does not.
Therefore, take them apart.
The MX25U25643G has been tested by ch341a programmer : read, write, erase and wp.
We have tested --wp-enable, --wp-disable, --wp-list and --wp-range
commands for write-protect feature.
MX25U25643G datasheet is available at the following URL:
https://www.mxic.com.tw/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spe…
MX25U25635F datasheet is available at the following URL:
https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/sp…
Change-Id: I43de9ed123b9736c04d070754bcf9c32be5697ad
Signed-off-by: rogeryou <rogeryou(a)mxic.com.cn>
---
M doc/contact.rst
M doc/dev_guide/development_guide.rst
M doc/index.rst
A doc/release_notes/index.rst
A doc/release_notes/v_1_3.rst
A doc/user_docs/example_partial_wp.rst
A doc/user_docs/fw_updates_vs_spi_wp.rst
A doc/user_docs/index.rst
M flashchips.c
9 files changed, 599 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/42/78142/3
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/78188?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: doc: Make Time of Meeting more consistent
......................................................................
doc: Make Time of Meeting more consistent
Change-Id: I8b37d2913750946c71908e94fcd3041766f1b59d
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78188
Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M doc/contact.rst
1 file changed, 7 insertions(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Anastasia Klimchuk: Looks good to me, approved
diff --git a/doc/contact.rst b/doc/contact.rst
index 5bcac3f..57a9390 100644
--- a/doc/contact.rst
+++ b/doc/contact.rst
@@ -111,19 +111,19 @@
also known as
- | Wednesday 13.00-14.00 Pacific Standard Time UTC-8
- | Wednesday 22.00-23.00 Central European Time UTC+1
- | Thursday 8.00-9.00am Australian Eastern Daylight Time UTC+11
+ | Wednesday 13:00-14:00 Pacific Standard Time UTC-8
+ | Wednesday 22:00-23:00 Central European Time UTC+1
+ | Thursday 8:00-9:00 Australian Eastern Daylight Time UTC+11
Between April and September (inclusive)
- **Thursday 6.00-7.00am UTC+0**
+ **Thursday 6:00-7:00 UTC+0**
also known as
- | Wednesday 11pm-midnight Pacific Daylight Time UTC-7
- | Thursday 8.00-9.00am Central European Summer Time UTC+2
- | Thursday 16.00-17.00 Australian Eastern Standard Time UTC+10
+ | Wednesday 23:00-midnight Pacific Daylight Time UTC-7
+ | Thursday 8:00-9:00 Central European Summer Time UTC+2
+ | Thursday 16:00-17:00 Australian Eastern Standard Time UTC+10
The last week of March and 4 weeks of October there are no meetings
This is because daylight saving time changes are happening on different dates in different locations, and setting up meeting time becomes too complicated.
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Hsuan-ting Chen has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77887?usp=email )
Change subject: flashrom_tester: Align WP output format with upstream
......................................................................
Patch Set 2: Code-Review+1
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Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/78116?usp=email )
Change subject: doc: Convert release notes for v1.3
......................................................................
doc: Convert release notes for v1.3
Change-Id: I5b66a957249c3025715eff2b00f1be9eb0d36096
Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/78116
Reviewed-by: Alexander Goncharov <chat(a)joursoir.net>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M doc/index.rst
A doc/release_notes/index.rst
A doc/release_notes/v_1_3.rst
3 files changed, 222 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Alexander Goncharov: Looks good to me, approved
diff --git a/doc/index.rst b/doc/index.rst
index 3a303e1..8217056 100644
--- a/doc/index.rst
+++ b/doc/index.rst
@@ -13,6 +13,7 @@
user_docs/index
classic_cli_manpage
contact
+ release_notes/index
about_flashrom/index
how_to_add_docs
documentation_license
diff --git a/doc/release_notes/index.rst b/doc/release_notes/index.rst
new file mode 100644
index 0000000..a8ef58f
--- /dev/null
+++ b/doc/release_notes/index.rst
@@ -0,0 +1,7 @@
+Release notes
+=============
+
+.. toctree::
+ :maxdepth: 1
+
+ v_1_3
diff --git a/doc/release_notes/v_1_3.rst b/doc/release_notes/v_1_3.rst
new file mode 100644
index 0000000..d722566
--- /dev/null
+++ b/doc/release_notes/v_1_3.rst
@@ -0,0 +1,214 @@
+===============
+v1.3 (Feb 2023)
+===============
+
+It has been almost three years since our last release. All this time we have been working
+on enhancing the flashrom code base. This new release comes with a lot of new features, programmers,
+improvements, and bug fixes. A detailed but not exhaustive change log is presented below.
+
+New major user-visible features
+===============================
+
+* Support for the Linux I2C subsystem
+* Option to read/write only region to/from ROM is renamed to :code:`--include` (:code:`--image` option
+ is deprecated and exist only for back compatibility). An optional sub-parameter
+ (:code:`--include <region>[:<file>]`) to allow building the image to be written from multiple files is added
+* Support different SPI modes (Dual IO, Quad IO, Normal, Fast Read) for AMD’s chipsets (>= Bolton)
+* Support for Write Protection configuration (:code:`--wp-disable`, :code:`--wp-enable`, :code:`--wp-list`,
+ :code:`--wp-status`, :code:`--wp-range`, :code:`--wp-region`)
+* Add SPI SR2/SR3 read/write support
+* The Intel chipset detection has been improved
+* Bus Pirate SPI
+
+ * New parameter to control the external Vcc state (:code:`psus=<on|off>`)
+
+* Dediprog
+
+ * Add 4BA support on SF600 protocol version 3
+
+* Dummyflasher
+
+ * New parameter to allows emulating a bus/chip frequency (:code:`freq`)
+ * New parameter to emulate flash erase with either 0x00 or 0xff (:code:`erase_to_zero`)
+ * Add emulation for S25FL128L chip
+ * SR2, SR3 and WP is emulated for W25Q128FV
+ * Emulate variable-size SPI flash chip (4-byte address format is supported)
+
+* FT2232 SPI dongles
+
+ * New parameter to search FTDI by description, i.e. product string (:code:`description`)
+
+* SEGGER J-Link and compatible devices
+
+ * New parameter to active the 5V power supply during a flash operation (:code:`power`)
+
+* Drop "Promontory" architecture (AMD) support
+* End Of Life (EOL) for ITE IT85* specific code
+* README and man page updated with additional information
+
+The greatest increase in the speed of operations can be seen on the following programmers:
+SPI on Intel NICs, FT2232 SPI dongles
+
+Libflashrom
+===========
+
+* Add Write Protect functions to the API
+* Add rust Foreign Function Interface bindings for the libflashrom API
+* Move documentation from source file to header
+* Drop :code:`flashrom_system_info()`
+* Drop :code:`flashrom_supported_programmers()`
+* Add :code:`flashrom_layout_get_region_range()`
+* Declaration change from :code:`flashrom_layout_read_fmap_from_rom(struct flashrom_layout **const, struct flashctx *const, off_t, size_t)`
+ to :code:`flashrom_layout_read_fmap_from_rom(struct flashrom_layout **const, struct flashctx *const, size_t, size_t)`
+* Allow NULL-pointer argument in :code:`flashrom_flash_release()`
+
+Infrastructure expansion
+========================
+
+* Add blackbox test uber-script
+* Add E2E tester for a specific chip/chipset combo
+* Build script for Jenkins was upgraded and move to repository - :code:`test_build.sh`
+* Add a set of Dockerfiles for build testing - :code:`util/manibuilder`
+* Add a Nix shell file which is able to compile flashrom - :code:`util/shell.nix`
+* Add CMocka unit-test infrastructure into the meson build system (test for drivers available only
+ if its driver is built). The following tests are included:
+
+ * Core logic tests
+ * Basic lifecycle for :code:`dediprog`, :code:`nicrealtek`, :code:`raiden_debug_spi`, :code:`parade_lspcon`,
+ :code:`mediatek_i2c_spi`, :code:`realtek_mst_i2c_spi`
+ * Basic lifecycle + chip probe for :code:`dummyflasher`, :code:`linux_mtd`, :code:`linux_spi`
+ * Layout tests (overlapping, sanity checks, invalid range/address)
+ * Erasing/reading/writing/verifying chip tests
+ * Write Protect tests
+ * And others!
+
+* Introduce :code:`MAINTAINERS` file
+* Rename :code:`z60_flashrom.rules` to :code:`flashrom_udev.rules`
+* Introduce linter for git sign-off-by line
+* Move all header files to the new :code:`include` directory.
+
+Meson
+-----
+
+The minimum version has been increased. Requires at least :code:`0.53.0`.
+
+* Added build instructions - :code:`Documentation/building.md`
+* Allow libflashrom to be built as a static or shared library.
+* Add new options: :code:`print_wiki`, :code:`ich_descriptors_tool`, :code:`classic_cli`
+* Rename :code:`print_wiki` to :code:`classic_cli_print_wiki` option
+* Install the man file
+* Fix compilation under uClibc-ng
+* Add missing config option for J-Link SPI
+* Treat warnings as errors and use the same warning options as in Makefile.
+
+Makefile
+--------
+
+* Add support for Elbrus (e2k) architecture
+* Make pkg-config mandatory to find :code:`libftdi1`, :code:`libjaylink`,
+ :code:`libusb1`, :code:`libpci`
+ (you still can override detection and set cflags and ldflags manually)
+* Merge :code:`compiler`, :code:`hwlibs`, :code:`features` targets into :code:`config` target
+* Drop :code:`distclean` target
+* Drop STANDALONE mode
+* Summarize systems with the same CPPFLAGS and LDFLAGS
+* Only enable I2C programmers on Linux (linux-specific code)
+* Revise C compiler check, utsname and clock_gettime test, detection of Linux specific headers
+* Since the NI-845x is a Windows only proprietary library, disable it by default.
+* Enable the internal programmer on x86 or linux.
+* Fix building on AArch64 NixOS
+
+Various broken and missing dependencies have been fixed for these two build systems.
+
+New programmers
+===============
+
+* Chrome EC based debug tools - SuzyQable, Servo V4, C2D2 & uServo
+* Realtek RTD2142 MST
+* Parade lspcon USB-C to HDMI protocol translator
+* DirtyJTAG (a USB-JTAG firmware for STM32 MCUs)
+* MediaTek LCD controller
+* Programmers based on FT4233H FTDI
+* Kristech KT-LINK
+* Variants of STLINK-V3: STLINK-V3E, STLINK-V3S, STLINK-V3 With dual VCP, STLINK-V3 Without MSD
+* Intel Gemini Lake PCH
+* Intel Meteor Lake PCH
+* Intel Elkhart Lake PCH
+* Intel Emmitsburg PCH
+* Intel Comet Lake-U/400-series PCH
+* Intel Tiger Point/500-series PCH
+* Intel Jasper Lake PCH
+* Intel Alder Lake/600-series PCH
+* Intel PCH7 Desktop/Mobile/SFF Sample
+* More Intel PCHs variants (Apollo Lake, Cannon Point, Union Point, Lewisburg)
+
+At some point, flashrom supported ENE LPC interface keyboard controller and Microchip MEC1308 embedded controller.
+But they were dropped before the release because the code was no longer maintained by anyone. If you're interested,
+take a look at git history.
+
+New Boards
+==========
+
+* ASUS P3B-F
+* Jetway P4MDPT
+* ASUS P5W DH Deluxe
+
+New chips
+=========
+
+* AT25SF128A
+* B.25D16A
+* BY25Q128AS
+* FM25F01
+* FM25F02(A)
+* FM25F04(A)
+* FM25F005
+* FM25Q08
+* FM25Q16
+* FM25Q32
+* F29C51001B
+* GD25LQ128E
+* GD25Q256E
+* GD25WQ80E
+* MX25L12833F
+* MX25L12873F
+* MX25L3233F
+* MX25L5121E
+* MX25R3235F
+* MX66L1G45G
+* S25FL128L
+* S25FL128S
+* S25FL129P
+* S25FL256L
+* S25FL256S
+* S25FS128S
+* S29C51001B
+* V29C51001B
+* W25Q32JW...M
+* W25Q64JV
+* W25Q64JW...M
+* W25Q256JW
+* W25Q256JW_DTR
+* W25Q512JV
+* W25Q512NW-IM
+* W25X05(CL)
+* XM25QU64C
+* XM25QU128C
+* XM25QU256C
+* XM25QH64C
+* XM25QH128C
+* XM25QH256C
+
+Download
+========
+
+flashrom 1.3 can be downloaded in various ways:
+
+Anonymous checkout from the git repository at `<https://review.coreboot.org/flashrom.git>`_ (tag v1.3.0)
+
+A tarball is available for download at
+
+`<https://download.flashrom.org/releases/flashrom-v1.3.0.tar.bz2>`_ (GPG signature),
+fingerprint: :code:`6E6E F9A0 BA47 8006 E277 6E4C C037 BB41 3134 D111`
+
+and more in the "Tags" section of CGit at `<https://review.coreboot.org/cgit/flashrom.git>`_
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77999?usp=email )
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Also, maybe you can add a test for target=1 and 2?
See existing tests here:
tests/raiden_debug_spi.c
Thank you!
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Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77999?usp=email )
Change subject: raiden: Support target index with generic REQ_ENABLE
......................................................................
Patch Set 2:
(6 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/77999/comment/c52412b0_b232915d :
PS2, Line 42: target=1
Since these are new values for `target` param, please document it on the manpage, here:
doc/classic_cli_manpage.rst
https://review.coreboot.org/c/flashrom/+/77999/comment/85410071_f9a4b2f8 :
PS2, Line 45: archieves
achieves (typo)
https://review.coreboot.org/c/flashrom/+/77999/comment/c94080aa_f2975417 :
PS2, Line 48: run flashrom with HyperDebug
Could you please list the exact commands that you ran?
I read the commit message (thank you for providing so many details), and it would be ideal to run flashrom with both new and old values of `target` param. Run and then add to commit message, thank you!
Patchset:
PS2:
Jes, thank you for the patch! I have few comments.
File raiden_debug_spi.c:
https://review.coreboot.org/c/flashrom/+/77999/comment/a675bd52_f8e5f8d6 :
PS2, Line 1596: request_enable & 0xFF
Does this still work for target values EC and AP ?
https://review.coreboot.org/c/flashrom/+/77999/comment/e9c85ba6_949f29ce :
PS2, Line 1596: request_enable & 0xFF,
: (request_enable >> 8) & 0xFF,
A question: why do you initialise `request_enable` to a value that you never use by itself, just as `request_enable`? I see it is used as `request_enable & 0xFF` and as `(request_enable >> 8) & 0xFF` but never by itself?
What is the meaning of `request_enable` ?
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Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78069?usp=email )
Change subject: flashchips: Mark Atmel AT29C010A chip as tested for write operation
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Patch Set 1: Code-Review+2
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Change subject: raiden: Support target index with generic REQ_ENABLE
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Patch Set 2: Code-Review+2
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