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[XS] Change in flashrom[main]: Makefile: Fix version string for non-Git builds
by Anton Samsonov (Code Review) 20 Nov '23

20 Nov '23

Anton Samsonov has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/79152?usp=email ) Change subject: Makefile: Fix version string for non-Git builds ...................................................................... Makefile: Fix version string for non-Git builds Change-Id: I8694e618878823a9e96b1f2bcfa63f6c71d3c2ed --- M Makefile 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/79152/1 diff --git a/Makefile b/Makefile index bf01d0f..08ace29 100644 --- a/Makefile +++ b/Makefile @@ -392,8 +392,10 @@ VERSION ?= $(shell cat ./VERSION) VERSION_GIT ?= $(shell git describe 2>/dev/null) -ifdef VERSION_GIT +ifneq ($(VERSION_GIT),) VERSION := "$(VERSION) (git:$(VERSION_GIT))" +else + VERSION := "$(VERSION)" endif # No spaces in release names unless set explicitly -- To view, visit https://review.coreboot.org/c/flashrom/+/79152?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I8694e618878823a9e96b1f2bcfa63f6c71d3c2ed Gerrit-Change-Number: 79152 Gerrit-PatchSet: 1 Gerrit-Owner: Anton Samsonov <devel(a)zxlab.ru> Gerrit-MessageType: newchange

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[M] Change in flashrom[main]: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E
by Anastasia Klimchuk (Code Review) 20 Nov '23

20 Nov '23

Anastasia Klimchuk has submitted this change. ( https://review.coreboot.org/c/flashrom/+/78348?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E ...................................................................... flashchips: Split GD25Q127C/GD25Q128C and add GD25Q128E Q127C and Q128C are not the same. Q127C doesn't support QPI but Q128C does. So we need to split the existing GD25Q127C/GD25Q128C into two separated entries. We also introduce the new flashchip Q128E and merge it into Q127C. Datasheets: Q128E: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… Q127C: https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20220714/DS-0… Q128C: https://www.endrich.com/sixcms/media.php/2/GD25Q128C-Rev2.pdf Q128E and Q127C/Q128C have compatible main functions, their differences are: * Q128E uses 55 nm process, while Q127C/Q128C use 65nm * Q128E/Q127C does not support QPI * Q128E/Q127C have OTP: 3072B, while Q128C are 1536B * Q128E's fast read clock frequency is 133MHz, while Q127C/Q128C are 104MHZ So we decided to merge Q128E into Q127C. We also tested that Q128E could pass flashrom_tester while probing it as 127C/128C, so the main functionalities are compatible. Change the chip name from GD25Q127C/GD25Q128C to two entries GD25Q127C/GD25Q128E and GD25Q128C to make it more accurate. Chip revision history: - The 'GD25Q127C/GD25Q128C' definition was added in `commit e0c7abf219b81ad049d09a4671ebc9196153d308` as 'GD25Q128C' and later renamed to 'GD25Q127C/GD25Q128C' BUG=b:304863141, b:293545382 BRANCH=none TEST=flashrom_tester with flashrom binary could pass with Q128E, which contains probe, read, write, erase, and write protect Signed-off-by: Hsuan Ting Chen <roccochen(a)google.com> Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 Reviewed-on: https://review.coreboot.org/c/flashrom/+/78348 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c M include/flashchips.h 2 files changed, 52 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index 9fde98b..a4605bd 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6792,7 +6792,57 @@ { .vendor = "GigaDevice", - .name = "GD25Q127C/GD25Q128C", + .name = "GD25Q127C/GD25Q128E", + .bustype = BUS_SPI, + .manufacture_id = GIGADEVICE_ID, + .model_id = GIGADEVICE_GD25Q128, + .total_size = 16384, + .page_size = 256, + /* OTP: 3072B total; read 0x48; write 0x42, erase 0x44 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2, + .tested = TEST_OK_PREWB, + .probe = PROBE_SPI_RDID, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 4096} }, + .block_erase = SPI_BLOCK_ERASE_20, + }, { + .eraseblocks = { {32 * 1024, 512} }, + .block_erase = SPI_BLOCK_ERASE_52, + }, { + .eraseblocks = { {64 * 1024, 256} }, + .block_erase = SPI_BLOCK_ERASE_D8, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_60, + }, { + .eraseblocks = { {16 * 1024 * 1024, 1} }, + .block_erase = SPI_BLOCK_ERASE_C7, + } + }, + /* TODO: 2nd status reg (read 0x35, write 0x31) and 3rd status reg (read 0x15, write 0x11) */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, + .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, + .write = SPI_CHIP_WRITE256, + .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {2700, 3600}, + .reg_bits = + { + .srp = {STATUS1, 7, RW}, + .srl = {STATUS2, 0, RW}, + .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}}, + .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */ + .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */ + .cmp = {STATUS2, 6, RW}, + }, + .decode_range = DECODE_RANGE_SPI25, + }, + + { + .vendor = "GigaDevice", + .name = "GD25Q128C", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q128, diff --git a/include/flashchips.h b/include/flashchips.h index 1150ff5..17a6fc4 100644 --- a/include/flashchips.h +++ b/include/flashchips.h @@ -390,7 +390,7 @@ #define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */ #define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */ #define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */ -#define GIGADEVICE_GD25Q128 0x4018 /* GD25Q128B and GD25Q128C only, can be distinguished by SFDP */ +#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C, and GD25Q128E, can be distinguished by SFDP */ #define GIGADEVICE_GD25Q256D 0x4019 #define GIGADEVICE_GD25VQ21B 0x4212 #define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */ -- To view, visit https://review.coreboot.org/c/flashrom/+/78348?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I3300671b1cf74b3ea0469b9c5a833489ab4914f5 Gerrit-Change-Number: 78348 Gerrit-PatchSet: 7 Gerrit-Owner: Hsuan-ting Chen <roccochen(a)google.com> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in flashrom[main]: tests: Add test cases for erasing/writing unaligned layout regions
by Peter Marheine (Code Review) 20 Nov '23

20 Nov '23

Attention is currently required from: Aarya, Alexander Goncharov, Anastasia Klimchuk. Peter Marheine has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78985?usp=email ) Change subject: tests: Add test cases for erasing/writing unaligned layout regions ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/78985?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I726a30b0e47a966e8093ddc19abf4a65fb1d70ce Gerrit-Change-Number: 78985 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Sun, 19 Nov 2023 23:13:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in flashrom[main]: flashchips: change print lock status funcs for Winbond chips
by Alexander Goncharov (Code Review) 18 Nov '23

18 Nov '23

Alexander Goncharov has submitted this change. ( https://review.coreboot.org/c/flashrom/+/75877?usp=email ) Change subject: flashchips: change print lock status funcs for Winbond chips ...................................................................... flashchips: change print lock status funcs for Winbond chips Decode status register bits for user friendly output. Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> Change-Id: I5066863b514825aee0dffe496492514ac99b6e49 Reviewed-on: https://review.coreboot.org/c/flashrom/+/75877 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> --- M flashchips.c 1 file changed, 21 insertions(+), 21 deletions(-) Approvals: Nikolai Artemiev: Looks good to me, approved build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, but someone else must approve diff --git a/flashchips.c b/flashchips.c index 17807c4..9fde98b 100644 --- a/flashchips.c +++ b/flashchips.c @@ -18384,7 +18384,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18433,7 +18433,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18483,7 +18483,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18531,7 +18531,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18581,7 +18581,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18712,7 +18712,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18767,7 +18767,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18822,7 +18822,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18877,7 +18877,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18924,7 +18924,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -18974,7 +18974,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19025,7 +19025,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19077,7 +19077,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19128,7 +19128,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19179,7 +19179,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19231,7 +19231,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19283,7 +19283,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19550,7 +19550,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19692,7 +19692,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -19742,7 +19742,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, /* TODO: improve */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -21218,7 +21218,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_PLAIN, + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT, .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, -- To view, visit https://review.coreboot.org/c/flashrom/+/75877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I5066863b514825aee0dffe496492514ac99b6e49 Gerrit-Change-Number: 75877 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in flashrom[main]: spi25_statusreg: rename amic_a25l032 print to a generic name
by Alexander Goncharov (Code Review) 18 Nov '23

18 Nov '23

Alexander Goncharov has submitted this change. ( https://review.coreboot.org/c/flashrom/+/78874?usp=email ) Change subject: spi25_statusreg: rename amic_a25l032 print to a generic name ...................................................................... spi25_statusreg: rename amic_a25l032 print to a generic name Other chips (at least Winbond) will benefit from this change. Also, drop the FIXME comment, as it can be misleading. The "pretty print" functions should only display values from the Status Register, so using an inappropriate function might only confuse user. Signed-off-by: Alexander Goncharov <chat(a)joursoir.net> Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804 Reviewed-on: https://review.coreboot.org/c/flashrom/+/78874 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm(a)chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev(a)google.com> --- M flashchips.c M include/flash.h M spi25_statusreg.c 3 files changed, 6 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Anastasia Klimchuk: Looks good to me, approved Nikolai Artemiev: Looks good to me, approved diff --git a/flashchips.c b/flashchips.c index d80a574..17807c4 100644 --- a/flashchips.c +++ b/flashchips.c @@ -745,7 +745,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_AMIC_A25L032, /* bit5: T/B, bit6: prot size */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: 2nd status reg (read with 0x35) */ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -1275,7 +1275,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_AMIC_A25L032, /* bit5: T/B, bit6: prot size */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: 2nd status reg (read with 0x35) */ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, @@ -1315,7 +1315,7 @@ .block_erase = SPI_BLOCK_ERASE_C7, } }, - .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_AMIC_A25L032, /* bit5: T/B, bit6: prot size */ + .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: 2nd status reg (read with 0x35) */ .write = SPI_CHIP_WRITE256, .read = SPI_CHIP_READ, diff --git a/include/flash.h b/include/flash.h index 4c08549..284461e 100644 --- a/include/flash.h +++ b/include/flash.h @@ -369,7 +369,6 @@ PRINTLOCK_W39V080A, PRINTLOCK_W39V080FA, PRINTLOCK_W39V080FA_DUAL, - SPI_PRETTYPRINT_STATUS_REGISTER_AMIC_A25L032, SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF, SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF_SEC, SPI_PRETTYPRINT_STATUS_REGISTER_AT25F, @@ -385,6 +384,7 @@ SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD, SPI_PRETTYPRINT_STATUS_REGISTER_BP2_SRWD, SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, + SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP, SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, SPI_PRETTYPRINT_STATUS_REGISTER_DEFAULT_WELWIP, diff --git a/spi25_statusreg.c b/spi25_statusreg.c index bb56ee1..98988af 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -601,16 +601,7 @@ return 0; } -/* === Amic === - * FIXME: spi_disable_blockprotect is incorrect but works fine for chips using - * spi_prettyprint_status_register_bp1_srwd or - * spi_prettyprint_status_register_bp2_srwd. - * FIXME: spi_disable_blockprotect is incorrect and will fail for chips using - * spi_prettyprint_status_register_amic_a25l032 if those have locks controlled - * by the second status register. - */ - -static int spi_prettyprint_status_register_amic_a25l032(struct flashctx *flash) +static int spi_prettyprint_status_register_srwd_sec_tb_bp2_welwip(struct flashctx *flash) { uint8_t status; int ret = spi_read_register(flash, STATUS1, &status); @@ -1056,7 +1047,6 @@ case PRINTLOCK_W39V080A: return &printlock_w39v080a; case PRINTLOCK_W39V080FA: return &printlock_w39v080fa; case PRINTLOCK_W39V080FA_DUAL: return &printlock_w39v080fa_dual; - case SPI_PRETTYPRINT_STATUS_REGISTER_AMIC_A25L032: return &spi_prettyprint_status_register_amic_a25l032; case SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF: return &spi_prettyprint_status_register_at25df; case SPI_PRETTYPRINT_STATUS_REGISTER_AT25DF_SEC: return &spi_prettyprint_status_register_at25df_sec; case SPI_PRETTYPRINT_STATUS_REGISTER_AT25F: return &spi_prettyprint_status_register_at25f; @@ -1072,6 +1062,7 @@ case SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD: return &spi_prettyprint_status_register_bp2_ep_srwd; case SPI_PRETTYPRINT_STATUS_REGISTER_BP2_SRWD: return &spi_prettyprint_status_register_bp2_srwd; case SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL: return &spi_prettyprint_status_register_bp2_tb_bpl; + case SPI_PRETTYPRINT_STATUS_REGISTER_SRWD_SEC_TB_BP2_WELWIP: return &spi_prettyprint_status_register_srwd_sec_tb_bp2_welwip; case SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD: return &spi_prettyprint_status_register_bp3_srwd; case SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD: return &spi_prettyprint_status_register_bp4_srwd; case SPI_PRETTYPRINT_STATUS_REGISTER_DEFAULT_WELWIP: return &spi_prettyprint_status_register_default_welwip; -- To view, visit https://review.coreboot.org/c/flashrom/+/78874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7169a2312698343e1065cdca91a3985e00cb3804 Gerrit-Change-Number: 78874 Gerrit-PatchSet: 2 Gerrit-Owner: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Nikolai Artemiev <nartemiev(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in flashrom[main]: erasure_layout: Fix unaligned region end offset by 1
by Anastasia Klimchuk (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Aarya, Alexander Goncharov. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78984?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: erasure_layout: Fix unaligned region end offset by 1 ...................................................................... Patch Set 2: (2 comments) Patchset: PS1: > The open question here is whether anything is needed for start region branch. […] I did more investigation to understand why no fix is needed for the case when start of the region is extended, and yes it seems no fix is needed for start region. The reason is that the functions used to handle the extension of the region boundaries, ours `read_flash` and not ours `memcpy`, they both are "start-inclusive". Now, for both start and end boundaries extension, diff is calculated correctly. But then, there is the code which handles the extended area, this area is outside of the initial layout. When start boundary is extended, the code works because `read_flash` and `memcpy` start from the first byte of extended area and go through its length. However, when end boundary is extended, we don't need to start from the last byte of the initial region, we need to start from the first byte after the initial region. Therefore +1 is needed for the end boundary processing. Patchset: PS2: After some investigation I came to conclusion that no fix is needed for start boundary extension (see my other comment). So I won't be adding more to this patch, unless there are other comments of course. Joursoir, is it possible for you to test the patch on the images that you initially found the bug in ticket 494? It would be great, since you initially reported the bug, so that you can confirm it is fixed. -- To view, visit https://review.coreboot.org/c/flashrom/+/78984?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I7f78a0090065cd2a952cba1a5d28179483ba4c55 Gerrit-Change-Number: 78984 Gerrit-PatchSet: 2 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Sat, 18 Nov 2023 10:36:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: tests: Add test cases for erasing/writing unaligned layout regions
by Anastasia Klimchuk (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Aarya, Alexander Goncharov, Peter Marheine. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/78985?usp=email ) Change subject: tests: Add test cases for erasing/writing unaligned layout regions ...................................................................... Patch Set 4: (2 comments) Patchset: PS4: I have modified test case #16 to heavily test extending the start of the unaligned region. Other test cases in this patch cover extending the end of unaligned region, and #19 has logical layout which is smaller than the total size of chip. File tests/erase_func_algo.c: https://review.coreboot.org/c/flashrom/+/78985/comment/abcb5b7a_f626eb52 : PS2, Line 30: /* How many small chip test cases. */ > Drop the comment too. […] Oh I completely missed! Done. -- To view, visit https://review.coreboot.org/c/flashrom/+/78985?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I726a30b0e47a966e8093ddc19abf4a65fb1d70ce Gerrit-Change-Number: 78985 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Comment-Date: Sat, 18 Nov 2023 09:58:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Marheine <pmarheine(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in flashrom[main]: tests: Add test cases for erasing/writing unaligned layout regions
by Anastasia Klimchuk (Code Review) 18 Nov '23

18 Nov '23

Attention is currently required from: Aarya, Alexander Goncharov, Anastasia Klimchuk, Peter Marheine. Hello Aarya, Alexander Goncharov, Peter Marheine, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/flashrom/+/78985?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Peter Marheine, Verified+1 by build bot (Jenkins) Change subject: tests: Add test cases for erasing/writing unaligned layout regions ...................................................................... tests: Add test cases for erasing/writing unaligned layout regions The test cases from #16 onwards cover the case when layout region is not aligned with eraseblock region, and therefore either layout start boundary or end boundary needs to be extended to align with eraseblock. Ticket: https://ticket.coreboot.org/issues/494 Change-Id: I726a30b0e47a966e8093ddc19abf4a65fb1d70ce Signed-off-by: Anastasia Klimchuk <aklm(a)flashrom.org> --- M tests/erase_func_algo.c 1 file changed, 118 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/78985/4 -- To view, visit https://review.coreboot.org/c/flashrom/+/78985?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I726a30b0e47a966e8093ddc19abf4a65fb1d70ce Gerrit-Change-Number: 78985 Gerrit-PatchSet: 4 Gerrit-Owner: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Reviewer: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aarya <aarya.chaumal(a)gmail.com> Gerrit-Attention: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-Attention: Peter Marheine <pmarheine(a)chromium.org> Gerrit-Attention: Alexander Goncharov <chat(a)joursoir.net> Gerrit-MessageType: newpatchset

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[S] Change in flashrom[main]: serial: Fix sp_flush_incoming for serprog TCP connections
by Name of user not set (Code Review) 17 Nov '23

17 Nov '23

Name of user not set #1005208 has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/79112?usp=email ) Change subject: serial: Fix sp_flush_incoming for serprog TCP connections ...................................................................... serial: Fix sp_flush_incoming for serprog TCP connections I was working on an esp32 serprog-compatible SPI programmer pet project, and when i implemented the TCP over Wi-Fi for serprog, i discovered that sp_flush_incoming() silently fails if the underlying sp_fd descriptor is a TCP socket. I added a check for this case - tcflush returns ENOTTY, meaning tcflush is not supported for not terminal objects, in this case a fallback serialport_read_nonblock loop is used. After that i was able to communicate with my serprog programmer implementation over TCP with 100% success rate. Signed-off-by: Stanislav Ponomarev <me(a)stasponomarev.com> Change-Id: I9724a2fcd4a41dede2c15f83877efa6c3b0b7fae --- M serial.c 1 file changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/12/79112/1 diff --git a/serial.c b/serial.c index 10d739a..f9bd280 100644 --- a/serial.c +++ b/serial.c @@ -377,8 +377,25 @@ #if IS_WINDOWS PurgeComm(sp_fd, PURGE_RXCLEAR); #else - /* FIXME: error handling */ - tcflush(sp_fd, TCIFLUSH); + int ret = tcflush(sp_fd, TCIFLUSH); + if (ret == 0) + return; + + // TCP socket case: sp_fd is not a terminal descriptor - tcflush is not supported + if (errno == ENOTTY) + { + unsigned char c; + + while ((ret = serialport_read_nonblock(&c, 1, 1, NULL)) == 0); + + if (ret > 0) // no more data available + return; + + msg_perr("Could not flush serial port incoming buffer: read has failed"); + return; + } + + msg_perr_strerror("Could not flush serial port incoming buffer: "); #endif return; } -- To view, visit https://review.coreboot.org/c/flashrom/+/79112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: I9724a2fcd4a41dede2c15f83877efa6c3b0b7fae Gerrit-Change-Number: 79112 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1005208 Gerrit-MessageType: newchange

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[S] Change in flashrom[main]: Remove dependency on C23 __has_include()
by Anastasia Klimchuk (Code Review) 17 Nov '23

17 Nov '23

Attention is currently required from: Anton Samsonov, Thomas Heijligen. Anastasia Klimchuk has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/77089?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Remove dependency on C23 __has_include() ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Sorry for such a long delay in response, but finally I got back to this patch, and wow it looks so much better, thank you! :) I only want to ask add testing info in commit message. I understand you have tested both makefile and meson, but better have the info in commit message. Also if you have tested on different environments (with or without headers), you can list environments that you tested on. -- To view, visit https://review.coreboot.org/c/flashrom/+/77089?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: main Gerrit-Change-Id: Ic544963ffd29626ae0a21bdddb1c78850cc43ec6 Gerrit-Change-Number: 77089 Gerrit-PatchSet: 4 Gerrit-Owner: Anton Samsonov <devel(a)zxlab.ru> Gerrit-Reviewer: Alexander Goncharov <chat(a)joursoir.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anastasia Klimchuk <aklm(a)chromium.org> Gerrit-CC: Anton Samsonov <avscomputing(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Thomas Heijligen <src(a)posteo.de> Gerrit-Attention: Anton Samsonov <devel(a)zxlab.ru> Gerrit-Comment-Date: Fri, 17 Nov 2023 10:05:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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