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Change in flashrom[staging]: spi25: Enable direct 4BA read and write using feature bits
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22021 Change subject: spi25: Enable direct 4BA read and write using feature bits ...................................................................... spi25: Enable direct 4BA read and write using feature bits Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M flashchips.c M spi25.c 3 files changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/21/22021/1 diff --git a/flash.h b/flash.h index a3e7fd4..5538955 100644 --- a/flash.h +++ b/flash.h @@ -121,6 +121,8 @@ #define FEATURE_QPI (1 << 9) #define FEATURE_4BA_SUPPORT (1 << 10) #define FEATURE_4BA_EXT_ADDR (1 << 11) +#define FEATURE_4BA_READ (1 << 12) +#define FEATURE_4BA_WRITE (1 << 13) enum test_state { OK = 0, diff --git a/flashchips.c b/flashchips.c index 742cc6e..9848e5e 100644 --- a/flashchips.c +++ b/flashchips.c @@ -9752,7 +9752,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ | FEATURE_4BA_WRITE, .four_bytes_addr_funcs = { .read_nbyte = spi_nbyte_read_4ba_direct, @@ -9791,7 +9791,7 @@ .page_size = 256, /* supports SFDP */ /* OTP: 64B total; read 0x4B, write 0x42 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ | FEATURE_4BA_WRITE, .four_bytes_addr_funcs = { .read_nbyte = spi_nbyte_read_4ba_direct, @@ -14675,7 +14675,7 @@ /* supports SFDP */ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* FOUR_BYTE_ADDR: supports 4-bytes addressing mode */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT, + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_SUPPORT | FEATURE_4BA_READ, .four_bytes_addr_funcs = { .set_4ba = spi_enter_4ba_b7_we, /* enter 4-bytes addressing mode by CMD B7 + WREN */ diff --git a/spi25.c b/spi25.c index 052c6f3..dcab177 100644 --- a/spi25.c +++ b/spi25.c @@ -577,13 +577,21 @@ static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) { - return spi_write_cmd(flash, JEDEC_BYTE_PROGRAM, addr, bytes, len, 10); + const uint8_t op = + flash->chip->feature_bits & FEATURE_4BA_WRITE + ? JEDEC_BYTE_PROGRAM_4BA + : JEDEC_BYTE_PROGRAM; + return spi_write_cmd(flash, op, addr, bytes, len, 10); } int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { - uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { JEDEC_READ, }; + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { + flash->chip->feature_bits & FEATURE_4BA_READ + ? JEDEC_READ_4BA + : JEDEC_READ, + }; const int addr_len = spi_prepare_address(flash, cmd, address); if (addr_len < 0) -- To view, visit https://review.coreboot.org/22021 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: I2f6817ca198bf923671a7aa67e956e5477d71848 Gerrit-Change-Number: 22021 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: spi4ba: Drop now obsolete redundant functions
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22023 Change subject: spi4ba: Drop now obsolete redundant functions ...................................................................... spi4ba: Drop now obsolete redundant functions Change-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M spi4ba.c 1 file changed, 0 insertions(+), 651 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/22023/1 diff --git a/spi4ba.c b/spi4ba.c index a44e067..d8ab6a8 100644 --- a/spi4ba.c +++ b/spi4ba.c @@ -121,246 +121,6 @@ return result; } -/* Program one flash byte from 4-bytes addressing mode */ -int spi_byte_program_4ba(struct flashctx *flash, unsigned int addr, uint8_t databyte) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE + 1, - .writearr = (const unsigned char[]){ - JEDEC_BYTE_PROGRAM, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - databyte - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X)\n", __func__, addr); - - result = spi_send_multicommand(flash, cmds); - if (result) - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; -} - -/* Program flash bytes from 4-bytes addressing mode */ -int spi_nbyte_program_4ba(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - int result; - unsigned char cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + 256] = { - JEDEC_BYTE_PROGRAM, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = (JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - if (!len) { - msg_cerr("%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - msg_cerr("%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[(JEDEC_BYTE_PROGRAM_OUTSIZE + 1) - 1], bytes, len); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -/* Read flash bytes from 4-bytes addressing mode */ -int spi_nbyte_read_4ba(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len) -{ - const unsigned char cmd[JEDEC_READ_OUTSIZE + 1] = { - JEDEC_READ, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - /* Send Read */ - return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); -} - -/* Erase one sector of flash from 4-bytes addressing mode */ -int spi_block_erase_20_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_SE_OUTSIZE + 1, - .writearr = (const unsigned char[]){ - JEDEC_SE, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - -/* Erase one sector of flash from 4-bytes addressing mode */ -int spi_block_erase_52_4ba(struct flashctx *flash, unsigned int addr, unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_52_OUTSIZE + 1, - .writearr = (const unsigned char[]){ - JEDEC_BE_52, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - -/* Erase one sector of flash from 4-bytes addressing mode */ -int spi_block_erase_d8_4ba(struct flashctx *flash, unsigned int addr, - unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE + 1, - .writearr = (const unsigned char[]){ - JEDEC_BE_D8, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - /* Write Extended Address Register value */ int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata) { @@ -394,417 +154,6 @@ return result; } return 0; -} - -/* Assign required value of Extended Address Register. This function - keeps last value of the register and writes the register if the - value has to be changed only. */ -int set_extended_address_register(struct flashctx *flash, uint8_t data) -{ - static uint8_t ext_addr_reg_state; /* memory for last register state */ - static int ext_addr_reg_state_valid = 0; - int result; - - if (ext_addr_reg_state_valid == 0 || data != ext_addr_reg_state) { - result = spi_write_extended_address_register(flash, data); - if (result) { - ext_addr_reg_state_valid = 0; - return result; - } - ext_addr_reg_state = data; - ext_addr_reg_state_valid = 1; - } - return 0; -} - -/* Program one flash byte using Extended Address Register - from 3-bytes addressing mode */ -int spi_byte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, - uint8_t databyte) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - databyte - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X)\n", __func__, addr); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -/* Program flash bytes using Extended Address Register - from 3-bytes addressing mode */ -int spi_nbyte_program_4ba_ereg(struct flashctx *flash, unsigned int addr, - const uint8_t *bytes, unsigned int len) -{ - int result; - unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - if (!len) { - msg_cerr("%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - msg_cerr("%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1], bytes, len); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -/* Read flash bytes using Extended Address Register - from 3-bytes addressing mode */ -int spi_nbyte_read_4ba_ereg(struct flashctx *flash, unsigned int addr, - uint8_t *bytes, unsigned int len) -{ - int result; - const unsigned char cmd[JEDEC_READ_OUTSIZE] = { - JEDEC_READ, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - /* Send Read */ - return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); -} - -/* Erases 4 KB of flash using Extended Address Register - from 3-bytes addressing mode */ -int spi_block_erase_20_4ba_ereg(struct flashctx *flash, unsigned int addr, - unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_SE_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_SE, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - -/* Erases 32 KB of flash using Extended Address Register - from 3-bytes addressing mode */ -int spi_block_erase_52_4ba_ereg(struct flashctx *flash, unsigned int addr, - unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_52_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_52, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - -/* Erases 64 KB of flash using Extended Address Register - from 3-bytes addressing mode */ -int spi_block_erase_d8_4ba_ereg(struct flashctx *flash, unsigned int addr, - unsigned int blocklen) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D8, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + blocklen - 1); - - result = set_extended_address_register(flash, (addr >> 24) & 0xff); - if (result) - return result; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; -} - -/* Program one flash byte with 4-bytes address from ANY mode (3-bytes or 4-bytes) - JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. - The presence of this instruction for an exact chip should be checked - by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ -int spi_byte_program_4ba_direct(struct flashctx *flash, unsigned int addr, - uint8_t databyte) -{ - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BYTE_PROGRAM_4BA, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - databyte - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X)\n", __func__, addr); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -/* Program flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) - JEDEC_BYTE_PROGRAM_4BA (12h) instruction is new for 4-bytes addressing flash chips. - The presence of this instruction for an exact chip should be checked - by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ -int spi_nbyte_program_4ba_direct(struct flashctx *flash, unsigned int addr, - const uint8_t *bytes, unsigned int len) -{ - int result; - unsigned char cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + 256] = { - JEDEC_BYTE_PROGRAM_4BA, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - if (!len) { - msg_cerr("%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - msg_cerr("%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[JEDEC_BYTE_PROGRAM_4BA_OUTSIZE - 1], bytes, len); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -/* Read flash bytes with 4-bytes address from ANY mode (3-bytes or 4-bytes) - JEDEC_READ_4BA (13h) instruction is new for 4-bytes addressing flash chips. - The presence of this instruction for an exact chip should be checked - by its datasheet or from SFDP 4-Bytes Address Instruction Table (JESD216B). */ -int spi_nbyte_read_4ba_direct(struct flashctx *flash, unsigned int addr, - uint8_t *bytes, unsigned int len) -{ - const unsigned char cmd[JEDEC_READ_4BA_OUTSIZE] = { - JEDEC_READ_4BA, - (addr >> 24) & 0xff, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff - }; - - msg_trace("-> %s (0x%08X-0x%08X)\n", __func__, addr, addr + len - 1); - - /* Send Read */ - return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); } /* Erase 4 KB of flash with 4-bytes address from ANY mode (3-bytes or 4-bytes) -- To view, visit https://review.coreboot.org/22023 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: I1d04448fd1acbfc37b8e17288f497a4292dfd6d6 Gerrit-Change-Number: 22023 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: spi25: Use common code for nbyte read/write and erase
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22019 Change subject: spi25: Use common code for nbyte read/write and erase ...................................................................... spi25: Use common code for nbyte read/write and erase Introduce spi_prepare_address() and spi_write_command() and use them in byte_program, nbyte_program, nbyte_read and erase procedures. The former abstracts over the address part of a SPI command to make it extensible for 4-byte adressing. spi_write_command() implements a simple WREN + write operation with address. It provides a common path to reduce overall redundancy. Also, reduce the polling delay in spi_block_erase_c4() from 500s to 500ms as the comment suggests. Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M chipdrivers.h M spi.h M spi25.c 3 files changed, 92 insertions(+), 429 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/19/22019/1 diff --git a/chipdrivers.h b/chipdrivers.h index 16a75a9..12fc5a3 100644 --- a/chipdrivers.h +++ b/chipdrivers.h @@ -55,8 +55,6 @@ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen); erasefunc_t *spi_get_erasefn_from_opcode(uint8_t opcode); int spi_chip_write_1(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len); -int spi_byte_program(struct flashctx *flash, unsigned int addr, uint8_t databyte); -int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len); int spi_nbyte_read(struct flashctx *flash, unsigned int addr, uint8_t *bytes, unsigned int len); int spi_read_chunked(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); int spi_write_chunked(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len, unsigned int chunksize); diff --git a/spi.h b/spi.h index de5b3be..41b0245 100644 --- a/spi.h +++ b/spi.h @@ -24,6 +24,8 @@ * Contains the generic SPI headers */ +#define JEDEC_MAX_ADDR_LEN 0x04 + /* Read Electronic ID */ #define JEDEC_RDID 0x9f #define JEDEC_RDID_OUTSIZE 0x01 diff --git a/spi25.c b/spi25.c index 4f8d497..f8ad692 100644 --- a/spi25.c +++ b/spi25.c @@ -323,6 +323,16 @@ return 0; } +static int spi_write_status(struct flashctx *const flash, const unsigned int poll_delay) +{ + /* FIXME: We can't tell if spi_read_status_register() failed. */ + /* FIXME: We don't time out. */ + while (spi_read_status_register(flash) & SPI_SR_WIP) + programmer_delay(poll_delay); + /* FIXME: Check the status register for errors. */ + return 0; +} + static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, const unsigned int poll_delay) { struct spi_command cmds[] = { @@ -340,13 +350,57 @@ if (result) msg_cerr("%s failed during command execution\n", __func__); - /* FIXME: We can't tell if spi_read_status_register() failed. */ - /* FIXME: We don't time out. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(poll_delay); - /* FIXME: Check the status register for errors. */ + const int status = spi_write_status(flash, poll_delay); - return result; + return result ? result : status; +} + +static int spi_prepare_address(struct flashctx *const flash, + uint8_t cmd_buf[], const unsigned int addr) +{ + /* TODO: extend for 4BA */ + cmd_buf[1] = (addr >> 16) & 0xff; + cmd_buf[2] = (addr >> 8) & 0xff; + cmd_buf[3] = (addr >> 0) & 0xff; + return 3; +} + +static int spi_write_cmd(struct flashctx *const flash, + const uint8_t op, const unsigned int addr, + const uint8_t *const out_bytes, const size_t out_len, + const unsigned int poll_delay) +{ + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN + 256]; + struct spi_command cmds[] = { + { + .writecnt = 1, + .writearr = (const unsigned char[]){ JEDEC_WREN }, + }, { + .writearr = cmd, + }, + NULL_SPI_CMD, + }; + + cmd[0] = op; + const int addr_len = spi_prepare_address(flash, cmd, addr); + if (addr_len < 0) + return 1; + + if (1 + addr_len + out_len > sizeof(cmd)) { + msg_cerr("%s called for too long a write\n", __func__); + return 1; + } + + memcpy(cmd + 1 + addr_len, out_bytes, out_len); + cmds[1].writecnt = 1 + addr_len + out_len; + + const int result = spi_send_multicommand(flash, cmds); + if (result) + msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); + + const int status = spi_write_status(flash, poll_delay); + + return result ? result : status; } int spi_chip_erase_60(struct flashctx *flash) @@ -370,43 +424,8 @@ int spi_block_erase_52(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_52_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_52, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0x52, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -414,42 +433,8 @@ */ int spi_block_erase_c4(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_C4_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_C4, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 240-480 s, so wait in 500 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(500 * 1000 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 240-480s, so wait in 500ms steps. */ + return spi_write_cmd(flash, 0xc4, addr, NULL, 0, 500 * 1000); } /* Block size is usually @@ -460,43 +445,8 @@ int spi_block_erase_d8(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D8_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D8, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0xd8, addr, NULL, 0, 100 * 1000); } /* Block size is usually @@ -505,207 +455,36 @@ int spi_block_erase_d7(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BE_D7_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_D7, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 100-4000 ms, so wait in 100 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 100-4000ms, so wait in 100ms steps. */ + return spi_write_cmd(flash, 0xd7, addr, NULL, 0, 100 * 1000); } /* Page erase (usually 256B blocks) */ int spi_block_erase_db(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_PE_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_PE, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - } }; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - - /* Wait until the Write-In-Progress bit is cleared. - * This takes up to 20 ms usually (on worn out devices up to the 0.5s range), so wait in 1 ms steps. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This takes up to 20ms usually (on worn out devices + up to the 0.5s range), so wait in 1ms steps. */ + return spi_write_cmd(flash, 0xdb, addr, NULL, 0, 1 * 1000); } /* Sector size is usually 4k, though Macronix eliteflash has 64k */ int spi_block_erase_20(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_SE_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_SE, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 15-800 ms, so wait in 10 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 15-800ms, so wait in 10ms steps. */ + return spi_write_cmd(flash, 0x20, addr, NULL, 0, 10 * 1000); } int spi_block_erase_50(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { -/* .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { */ - .writecnt = JEDEC_BE_50_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_50, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 10 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 10ms, so wait in 1ms steps. */ + return spi_write_cmd(flash, 0x50, addr, NULL, 0, 1 * 1000); } int spi_block_erase_81(struct flashctx *flash, unsigned int addr, unsigned int blocklen) { - int result; - struct spi_command cmds[] = { - { -/* .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { */ - .writecnt = JEDEC_BE_81_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BE_81, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff) - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", __func__, addr); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 8 ms, so wait in 1 ms steps. - */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 8ms, so wait in 1ms steps. */ + return spi_write_cmd(flash, 0x81, addr, NULL, 0, 1 * 1000); } int spi_block_erase_60(struct flashctx *flash, unsigned int addr, @@ -776,101 +555,22 @@ } } -int spi_byte_program(struct flashctx *flash, unsigned int addr, - uint8_t databyte) +static int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr & 0xff), - databyte - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; -} - -int spi_nbyte_program(struct flashctx *flash, unsigned int addr, const uint8_t *bytes, unsigned int len) -{ - int result; - /* FIXME: Switch to malloc based on len unless that kills speed. */ - unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + 256] = { - JEDEC_BYTE_PROGRAM, - (addr >> 16) & 0xff, - (addr >> 8) & 0xff, - (addr >> 0) & 0xff, - }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_BYTE_PROGRAM_OUTSIZE - 1 + len, - .writearr = cmd, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - if (!len) { - msg_cerr("%s called for zero-length write\n", __func__); - return 1; - } - if (len > 256) { - msg_cerr("%s called for too long a write\n", __func__); - return 1; - } - - memcpy(&cmd[4], bytes, len); - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution at address 0x%x\n", - __func__, addr); - } - return result; + return spi_write_cmd(flash, JEDEC_BYTE_PROGRAM, addr, bytes, len, 10); } int spi_nbyte_read(struct flashctx *flash, unsigned int address, uint8_t *bytes, unsigned int len) { - const unsigned char cmd[JEDEC_READ_OUTSIZE] = { - JEDEC_READ, - (address >> 16) & 0xff, - (address >> 8) & 0xff, - (address >> 0) & 0xff, - }; + uint8_t cmd[1 + JEDEC_MAX_ADDR_LEN] = { JEDEC_READ, }; + + const int addr_len = spi_prepare_address(flash, cmd, address); + if (addr_len < 0) + return 1; /* Send Read */ - return spi_send_command(flash, sizeof(cmd), len, cmd, bytes); + return spi_send_command(flash, 1 + addr_len, len, cmd, bytes); } /* @@ -981,7 +681,7 @@ for (i = start; i < start + len; i++) { result = (flash->chip->feature_bits & FEATURE_4BA_SUPPORT) == 0 - ? spi_byte_program(flash, i, buf[i - start]) + ? spi_nbyte_program(flash, i, buf + i - start, 1) : flash->chip->four_bytes_addr_funcs.program_byte(flash, i, buf[i - start]); if (result) return 1; @@ -999,30 +699,6 @@ unsigned char cmd[JEDEC_AAI_WORD_PROGRAM_CONT_OUTSIZE] = { JEDEC_AAI_WORD_PROGRAM, }; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_AAI_WORD_PROGRAM_OUTSIZE, - .writearr = (const unsigned char[]){ - JEDEC_AAI_WORD_PROGRAM, - (start >> 16) & 0xff, - (start >> 8) & 0xff, - (start & 0xff), - buf[0], - buf[1] - }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; switch (flash->mst->spi.type) { #if CONFIG_INTERNAL == 1 @@ -1050,14 +726,6 @@ if (spi_chip_write_1(flash, buf, start, start % 2)) return SPI_GENERIC_ERROR; pos += start % 2; - cmds[1].writearr = (const unsigned char[]){ - JEDEC_AAI_WORD_PROGRAM, - (pos >> 16) & 0xff, - (pos >> 8) & 0xff, - (pos & 0xff), - buf[pos - start], - buf[pos - start + 1] - }; /* Do not return an error for now. */ //return SPI_GENERIC_ERROR; } @@ -1069,14 +737,9 @@ //return SPI_GENERIC_ERROR; } - - result = spi_send_multicommand(flash, cmds); - if (result != 0) { - msg_cerr("%s failed during start command execution: %d\n", __func__, result); + result = spi_write_cmd(flash, JEDEC_AAI_WORD_PROGRAM, start, buf + pos - start, 2, 10); + if (result) goto bailout; - } - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10); /* We already wrote 2 bytes in the multicommand step. */ pos += 2; @@ -1090,8 +753,8 @@ msg_cerr("%s failed during followup AAI command execution: %d\n", __func__, result); goto bailout; } - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(10); + if (spi_write_status(flash, 10)) + goto bailout; } /* Use WRDI to exit AAI mode. This needs to be done before issuing any other non-AAI command. */ -- To view, visit https://review.coreboot.org/22019 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc1ae48acbfbd427a30bcd64bdc080dc3dc20503 Gerrit-Change-Number: 22019 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: spi25: Add native 4BA support
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22020 Change subject: spi25: Add native 4BA support ...................................................................... spi25: Add native 4BA support Allow 4-byte adresses, cache the upper most byte in flashctx if the chip uses an extended address register. Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M flashrom.c M spi25.c M spi4ba.h 4 files changed, 30 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/20/22020/1 diff --git a/flash.h b/flash.h index 52303f1..a3e7fd4 100644 --- a/flash.h +++ b/flash.h @@ -120,6 +120,7 @@ #define FEATURE_OTP (1 << 8) #define FEATURE_QPI (1 << 9) #define FEATURE_4BA_SUPPORT (1 << 10) +#define FEATURE_4BA_EXT_ADDR (1 << 11) enum test_state { OK = 0, @@ -236,6 +237,7 @@ bool verify_after_write; bool verify_whole_chip; } flags; + int address_high_byte; }; /* Timing used in probe routines. ZERO is -2 to differentiate between an unset diff --git a/flashrom.c b/flashrom.c index 4f17382..62991d5 100644 --- a/flashrom.c +++ b/flashrom.c @@ -2232,6 +2232,8 @@ } } + flash->address_high_byte = -1; + return 0; } diff --git a/spi25.c b/spi25.c index f8ad692..052c6f3 100644 --- a/spi25.c +++ b/spi25.c @@ -355,14 +355,34 @@ return result ? result : status; } +static int spi_set_extended_address(struct flashctx *const flash, const uint8_t addr_high) +{ + if (flash->address_high_byte != addr_high && + spi_write_extended_address_register(flash, addr_high)) + return -1; + flash->address_high_byte = addr_high; + return 0; +} + static int spi_prepare_address(struct flashctx *const flash, uint8_t cmd_buf[], const unsigned int addr) { - /* TODO: extend for 4BA */ - cmd_buf[1] = (addr >> 16) & 0xff; - cmd_buf[2] = (addr >> 8) & 0xff; - cmd_buf[3] = (addr >> 0) & 0xff; - return 3; + if (flash->chip->feature_bits & FEATURE_4BA_SUPPORT && + !(flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR)) { + cmd_buf[1] = (addr >> 24) & 0xff; + cmd_buf[2] = (addr >> 16) & 0xff; + cmd_buf[3] = (addr >> 8) & 0xff; + cmd_buf[4] = (addr >> 0) & 0xff; + return 4; + } else { + if (flash->chip->feature_bits & FEATURE_4BA_EXT_ADDR && + spi_set_extended_address(flash, addr >> 24)) + return -1; + cmd_buf[1] = (addr >> 16) & 0xff; + cmd_buf[2] = (addr >> 8) & 0xff; + cmd_buf[3] = (addr >> 0) & 0xff; + return 3; + } } static int spi_write_cmd(struct flashctx *const flash, diff --git a/spi4ba.h b/spi4ba.h index 8a01792..a0316bc 100644 --- a/spi4ba.h +++ b/spi4ba.h @@ -114,5 +114,6 @@ int spi_block_erase_5c_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); int spi_block_erase_dc_4ba_direct(struct flashctx *flash, unsigned int addr, unsigned int blocklen); +int spi_write_extended_address_register(struct flashctx *flash, uint8_t regdata); #endif /* __SPI_4BA_H__ */ -- To view, visit https://review.coreboot.org/22020 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: I644600beaab9a571b97b67f7516abe571d3460c1 Gerrit-Change-Number: 22020 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in flashrom[staging]: spi25: Introduce spi_simple_write_cmd()
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22018 Change subject: spi25: Introduce spi_simple_write_cmd() ...................................................................... spi25: Introduce spi_simple_write_cmd() spi_simple_write_cmd() executes WREN plus a single byte write and polls WIP afterwards. It's used to replace current spi_erase_chip_*() imple- mentations. Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M flash.h M spi25.c 2 files changed, 29 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/22018/1 diff --git a/flash.h b/flash.h index dfda9d2..52303f1 100644 --- a/flash.h +++ b/flash.h @@ -369,6 +369,7 @@ const unsigned char *writearr; unsigned char *readarr; }; +#define NULL_SPI_CMD { 0, 0, NULL, NULL, } int spi_send_command(struct flashctx *flash, unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr); int spi_send_multicommand(struct flashctx *flash, struct spi_command *cmds); uint32_t spi_get_valid_read_addr(struct flashctx *flash); diff --git a/spi25.c b/spi25.c index 30b862f..4f8d497 100644 --- a/spi25.c +++ b/spi25.c @@ -22,6 +22,7 @@ * Contains the common SPI chip driver functions */ +#include <stddef.h> #include <string.h> #include "flash.h" #include "flashchips.h" @@ -322,114 +323,48 @@ return 0; } -int spi_chip_erase_60(struct flashctx *flash) +static int spi_simple_write_cmd(struct flashctx *const flash, const uint8_t op, const unsigned int poll_delay) { - int result; struct spi_command cmds[] = { { - .writecnt = JEDEC_WREN_OUTSIZE, + .writecnt = 1, .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, }, { - .writecnt = JEDEC_CE_60_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_60 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", - __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ + .writecnt = 1, + .writearr = (const unsigned char[]){ op }, + }, + NULL_SPI_CMD, + }; + + const int result = spi_send_multicommand(flash, cmds); + if (result) + msg_cerr("%s failed during command execution\n", __func__); + + /* FIXME: We can't tell if spi_read_status_register() failed. */ + /* FIXME: We don't time out. */ while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); + programmer_delay(poll_delay); /* FIXME: Check the status register for errors. */ - return 0; + + return result; +} + +int spi_chip_erase_60(struct flashctx *flash) +{ + /* This usually takes 1-85s, so wait in 1s steps. */ + return spi_simple_write_cmd(flash, 0x60, 1000 * 1000); } int spi_chip_erase_62(struct flashctx *flash) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_62_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_62 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", - __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 2-5 s, so wait in 100 ms steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(100 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 2-5s, so wait in 100ms steps. */ + return spi_simple_write_cmd(flash, 0x62, 100 * 1000); } int spi_chip_erase_c7(struct flashctx *flash) { - int result; - struct spi_command cmds[] = { - { - .writecnt = JEDEC_WREN_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_WREN }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = JEDEC_CE_C7_OUTSIZE, - .writearr = (const unsigned char[]){ JEDEC_CE_C7 }, - .readcnt = 0, - .readarr = NULL, - }, { - .writecnt = 0, - .writearr = NULL, - .readcnt = 0, - .readarr = NULL, - }}; - - result = spi_send_multicommand(flash, cmds); - if (result) { - msg_cerr("%s failed during command execution\n", __func__); - return result; - } - /* Wait until the Write-In-Progress bit is cleared. - * This usually takes 1-85 s, so wait in 1 s steps. - */ - /* FIXME: We assume spi_read_status_register will never fail. */ - while (spi_read_status_register(flash) & SPI_SR_WIP) - programmer_delay(1000 * 1000); - /* FIXME: Check the status register for errors. */ - return 0; + /* This usually takes 1-85s, so wait in 1s steps. */ + return spi_simple_write_cmd(flash, 0xc7, 1000 * 1000); } int spi_block_erase_52(struct flashctx *flash, unsigned int addr, -- To view, visit https://review.coreboot.org/22018 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: Ib244356fa471e15863b52e6037899d19113cb4a9 Gerrit-Change-Number: 22018 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: spi25_statusreg: Return defined value on failed RDSR
by Nico Huber (Code Review) 15 Oct '17

15 Oct '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22017 Change subject: spi25_statusreg: Return defined value on failed RDSR ...................................................................... spi25_statusreg: Return defined value on failed RDSR The interface of spi_read_status_register() is broken and can't return errors. Let's not return random stack data at least. Change-Id: I714b20001a5443bba665c2e0061ca14069777581 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M spi25_statusreg.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/17/22017/1 diff --git a/spi25_statusreg.c b/spi25_statusreg.c index 01a6862..05c7acf 100644 --- a/spi25_statusreg.c +++ b/spi25_statusreg.c @@ -117,8 +117,11 @@ /* Read Status Register */ ret = spi_send_command(flash, sizeof(cmd), sizeof(readarr), cmd, readarr); - if (ret) + if (ret) { msg_cerr("RDSR failed!\n"); + /* FIXME: We should propagate the error. */ + return 0; + } return readarr[0]; } -- To view, visit https://review.coreboot.org/22017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: newchange Gerrit-Change-Id: I714b20001a5443bba665c2e0061ca14069777581 Gerrit-Change-Number: 22017 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in flashrom[staging]: 4BA: Print power-up addressing mode for N25Q SPI flash chips
by build bot (Jenkins) (Code Review) 14 Oct '17

14 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20512 ) Change subject: 4BA: Print power-up addressing mode for N25Q SPI flash chips ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/772/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/695/ : SUCCESS -- To view, visit https://review.coreboot.org/20512 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I95f1a8182dd15ca024bbee2b6f7b0dad0d8dd8b3 Gerrit-Change-Number: 20512 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Ed Swierk <eswierk(a)skyportsystems.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Oct 2017 11:01:47 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: 4BA: Allow disabling 4-byte address mode for SPI flash
by build bot (Jenkins) (Code Review) 14 Oct '17

14 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20510 ) Change subject: 4BA: Allow disabling 4-byte address mode for SPI flash ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/770/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/693/ : SUCCESS -- To view, visit https://review.coreboot.org/20510 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I0b25309d731426940fc50956b744b681ab599e87 Gerrit-Change-Number: 20510 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Ed Swierk <eswierk(a)skyportsystems.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Oct 2017 11:01:44 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: 4BA: Add Micron N25Q/MT25QL 32MB and 64MB 3V SPI flash
by build bot (Jenkins) (Code Review) 14 Oct '17

14 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20511 ) Change subject: 4BA: Add Micron N25Q/MT25QL 32MB and 64MB 3V SPI flash ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/771/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/694/ : SUCCESS -- To view, visit https://review.coreboot.org/20511 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I3c130c5ecf4bcc7cf3b34257cb5fc3df523ce08b Gerrit-Change-Number: 20511 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Ed Swierk <eswierk(a)skyportsystems.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Oct 2017 11:01:44 +0000 Gerrit-HasComments: No

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Change in flashrom[staging]: 4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressing
by build bot (Jenkins) (Code Review) 14 Oct '17

14 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20509 ) Change subject: 4BA: Add spi_exit_4ba function to switch SPI flash to 3-byte addressing ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/flashrom-customrules/769/ : SUCCESS https://qa.coreboot.org/job/flashrom_gerrit/692/ : SUCCESS -- To view, visit https://review.coreboot.org/20509 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: staging Gerrit-MessageType: comment Gerrit-Change-Id: I553e7fb5028f35e14a3a81b3fa8903c1b321a223 Gerrit-Change-Number: 20509 Gerrit-PatchSet: 4 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Ed Swierk <eswierk(a)skyportsystems.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Tauner <stefan.tauner(a)gmx.at> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 14 Oct 2017 11:01:32 +0000 Gerrit-HasComments: No

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