david.hendricks(a)gmail.com has posted comments on this change. ( https://review.coreboot.org/22344 )
Change subject: linux_spi: Dynamically detect max buffer size
......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/22344/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/22344/1//COMMIT_MSG@9
PS1, Line 9: The max buffer size of the linux kernel's SPI device is a compile-time parameter.
: Read it on initialization and use it to inform the max transfer size. We allow
: up to 5 bytes for the SPI command. On master, SPI commands are always 4 bytes,
: but 4ba support will raise that to 5. Choosing 5 makes sure this will keep
long lines
https://review.coreboot.org/#/c/22344/1//COMMIT_MSG@12
PS1, Line 12: but 4ba support will raise that to 5. Choosing 5 makes sure this will keep
: working when 4ba support is merged.
4BA has been merged, so I updated the wording here.
https://review.coreboot.org/#/c/22344/1/linux_spi.c
File linux_spi.c:
https://review.coreboot.org/#/c/22344/1/linux_spi.c@138
PS1, Line 138: atoi(buf);
Updated to use strtol() and add some paranoid error checking.
https://review.coreboot.org/#/c/22344/1/linux_spi.c@141
PS1, Line 141: if (param_fd != -1)
: close(param_fd);
May as well put this in the else clause above.
--
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david.hendricks(a)gmail.com has uploaded a new patch set (#3) to the change originally created by David Hendricks. ( https://review.coreboot.org/22344 )
Change subject: linux_spi: Dynamically detect max buffer size
......................................................................
linux_spi: Dynamically detect max buffer size
The max buffer size of the linux kernel's SPI device is a compile-time
parameter. Read it on initialization and use it to inform the max
transfer size.
Change-Id: Ic541e548ced8488f074d388f1c92174cad123064
Signed-off-by: Keno Fischer <keno(a)juliacomputing.com>
Signed-off-by: David Hendricks <dhendricks(a)fb.com>
---
M linux_spi.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/22344/3
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22344
to look at the new patch set (#2).
Change subject: linux_spi: Dynamically detect max buffer size
......................................................................
linux_spi: Dynamically detect max buffer size
The max buffer size of the linux kernel's SPI device is a compile-time
parameter. Read it on initialization and use it to inform the max
transfer size. We allow up to 5 bytes for the SPI command. SPI
commands can be up to 5 bytes when using 4BA.
Change-Id: Ic541e548ced8488f074d388f1c92174cad123064
Signed-off-by: Keno Fischer <keno(a)juliacomputing.com>
---
M linux_spi.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/22344/2
--
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David Hendricks has uploaded this change for review. ( https://review.coreboot.org/22344
Change subject: linux_spi: Dynamically detect max buffer size
......................................................................
linux_spi: Dynamically detect max buffer size
The max buffer size of the linux kernel's SPI device is a compile-time parameter.
Read it on initialization and use it to inform the max transfer size. We allow
up to 5 bytes for the SPI command. On master, SPI commands are always 4 bytes,
but 4ba support will raise that to 5. Choosing 5 makes sure this will keep
working when 4ba support is merged.
Change-Id: Ic541e548ced8488f074d388f1c92174cad123064
Signed-off-by: Keno Fischer <keno(a)juliacomputing.com>
---
M linux_spi.c
1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/44/22344/1
diff --git a/linux_spi.c b/linux_spi.c
index e51fbc4..f7d9434 100644
--- a/linux_spi.c
+++ b/linux_spi.c
@@ -42,6 +42,7 @@
*/
static int fd = -1;
+static size_t max_kernel_buf_size = 4096;
static int linux_spi_shutdown(void *data);
static int linux_spi_send_command(struct flashctx *flash, unsigned int writecnt,
@@ -127,6 +128,19 @@
return 1;
}
+ /* Try to read the kernel's max bufsize */
+ char buf[10];
+ memset(buf, 0, sizeof(buf));
+ int param_fd = open("/sys/module/spidev/parameters/bufsiz", O_RDONLY);
+ if (param_fd == -1 || read(param_fd, &buf, sizeof(buf) - 1) == -1) {
+ msg_pwarn("%s: failed to retrieve kernel buffer size. Attempting to use default.\n", __func__);
+ } else {
+ max_kernel_buf_size = atoi(buf);
+ }
+
+ if (param_fd != -1)
+ close(param_fd);
+
register_spi_master(&spi_master_linux);
return 0;
@@ -182,14 +196,16 @@
static int linux_spi_read(struct flashctx *flash, uint8_t *buf,
unsigned int start, unsigned int len)
{
+ /* The size of the command and the buffer may add up to no more than max_kernel_buf_size.
+ At the moment the command size is at most 5 bytes, so allow the rest for the buffer. */
return spi_read_chunked(flash, buf, start, len,
- (unsigned int)getpagesize());
+ max_kernel_buf_size - 5);
}
static int linux_spi_write_256(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len)
{
return spi_write_chunked(flash, buf, start, len,
- ((unsigned int)getpagesize()) - 4);
+ max_kernel_buf_size - 5);
}
#endif // CONFIG_LINUX_SPI == 1
--
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David Hendricks has posted comments on this change. ( https://review.coreboot.org/22274 )
Change subject: ichspi: Disable software sequencing by default for Skylake
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
The Lewisburg datasheet seems to indicate that SCGO is RW, and I'm not aware of any C62x variants where that use a different datasheet. So I think we're safe there.
However, I haven't tested swseq on Lewisburg since, as you suggested, I don't have one with an unlocked/non-zero opmenu at the moment. Flashrom sees the missing opcodes and falls back to hwseq on my test system.
https://review.coreboot.org/#/c/22274/1/ichspi.c
File ichspi.c:
https://review.coreboot.org/#/c/22274/1/ichspi.c@1957
PS1, Line 1957: }
Would it make sense to move this to line 1800, closer to where ich_spi_mode gets set (near the beginning of case CHIPSET_ICH8)?
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Gerrit-Change-Number: 22274
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Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
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Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
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Gerrit-Comment-Date: Sun, 05 Nov 2017 01:51:34 +0000
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22338
to look at the new patch set (#2).
Change subject: Allow only "flashrom developers" to submit (on all branches).
......................................................................
Allow only "flashrom developers" to submit (on all branches).
Change-Id: I8dfc594c60292d03a36854f592c540e052c09c03
---
M project.config
1 file changed, 2 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/38/22338/2
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