Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/22274 )
Change subject: ichspi: Disable software sequencing by default for Skylake
......................................................................
ichspi: Disable software sequencing by default for Skylake
Skylake is a mess, especially with coreboot. We have now a present and
configured software sequencing interface with SCGO supposedly being
readonly (Apollo Lake has that feature and a strap documented, Skylake
behaviour might be the same). As we can't easily check if it's read-
only, just enable hardware sequencing by default (even if the software
sequencing interface seems usable).
Change-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Reviewed-on: https://review.coreboot.org/22274
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: David Hendricks <david.hendricks(a)gmail.com>
---
M ichspi.c
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
David Hendricks: Looks good to me, approved
diff --git a/ichspi.c b/ichspi.c
index ec81628..859d55f 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1951,6 +1951,11 @@
ich_spi_mode = ich_hwseq;
}
+ if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT) {
+ msg_pdbg("Enabling hardware sequencing by default for 100 series PCH.\n");
+ ich_spi_mode = ich_hwseq;
+ }
+
if (ich_spi_mode == ich_hwseq) {
if (!desc_valid) {
msg_perr("Hardware sequencing was requested "
--
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Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: merged
Gerrit-Change-Id: I8a13fb9c3ca679b3f7d39ad1dc56d5efdc80045b
Gerrit-Change-Number: 22274
Gerrit-PatchSet: 2
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
David Hendricks has posted comments on this change. ( https://review.coreboot.org/22344 )
Change subject: linux_spi: Dynamically detect max buffer size
......................................................................
Patch Set 4:
(5 comments)
Thanks for the quick (and thorough) review as always.
I ended up re-writing a significant portion of this patch. Assuming the changes look good, what's the "right" thing to do to get things merged? Merge everything in this patch, or split my updates into a follow-up patch?
https://review.coreboot.org/#/c/22344/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/22344/3//COMMIT_MSG@9
PS3, Line 9: Read max buffer size from sysfs if available.
:
> That's not true, and I can say that from this patch: If we
I guess the original author meant that it's a compile-time constant in the kernel? In any case, I went ahead and simplified this further to remove any possible confusion.
https://review.coreboot.org/#/c/22344/3/linux_spi.c
File linux_spi.c:
https://review.coreboot.org/#/c/22344/3/linux_spi.c@134
PS3, Line 134: fp = fopen(BUF_SIZE_FROM_SYSFS, "r");
> Isn't there a way to query this over the device interface?
Not sure... I don't see any other obvious way of getting at it. There's no ioctl for this AFAICT by looking thru the spidev documentation. The only clue seems to be:
- There's a limit on the number of bytes each I/O request can transfer to the SPI device. It defaults to one page, but that can be changed using a module parameter.
So either read the module parameter via sysfs or default to using getpagesize() which the code currently does.
https://review.coreboot.org/#/c/22344/3/linux_spi.c@135
PS3, Line 135: if (!fp) {
> What if read() returns a short byte count? What if it gets inter-
Done.
https://review.coreboot.org/#/c/22344/3/linux_spi.c@199
PS3, Line 199: The implementation currently does not support requests that
> Why? rx/tx buffers seem to be handled separately.
Re "why": As to not rely on the driver to split large transactions? I'm not if this is a big deal for spidev, but I have had issues with MTD in the past (https://chromium-review.googlesource.com/505409).
Re rx/tx being handled separately: Are you referring to the current (old) code? That may be an error, I think Keno was correct to handle read and write buffers the same and account for command size.
https://review.coreboot.org/#/c/22344/4/linux_spi.c
File linux_spi.c:
https://review.coreboot.org/#/c/22344/4/linux_spi.c@222
PS4, Line 222: *
oops, i'll fix this...
--
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Gerrit-Project: flashrom
Gerrit-Branch: staging
Gerrit-MessageType: comment
Gerrit-Change-Id: Ic541e548ced8488f074d388f1c92174cad123064
Gerrit-Change-Number: 22344
Gerrit-PatchSet: 4
Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: david.hendricks(a)gmail.com
Gerrit-Comment-Date: Sun, 05 Nov 2017 21:38:37 +0000
Gerrit-HasComments: Yes