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Hello Anastasia Klimchuk, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/69678?usp=email
to look at the new patch set (#2).
Change subject: flashchips: Add Macronix MX25R1635F
......................................................................
flashchips: Add Macronix MX25R1635F
16Mbit (2MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is
similar to the already-supported MX25R3235F, but the total size is
halved.
Tested probe, read, erase, write and verify with buspirate.
Datasheet: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8702/MX25R1635F,%20Wide…
Change-Id: Idce301ed90d6742b56e928068d201e5c3a2e5aee
Signed-off-by: Davide Gerhard <rainbow(a)irh.it>
---
M flashchips.c
M include/flashchips.h
2 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/69678/2
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Change subject: flashchips: Remove Macronix MX25U25635F from chip list
......................................................................
Patch Set 1:
(1 comment)
File flashchips.c:
https://review.coreboot.org/c/flashrom/+/79633/comment/39a8999d_cac946ee :
PS1, Line 10310: .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
> Hi, if WPSEL command is issued for MX25U25635F (older chip), it will be ignored.
In general, what Nikolai is saying is the right approach, and also it's a future-proof approach.
I understand this situation happens for the first time? (the situation being two chips of the same model ID, and the customer only wants the newest one). But realistically, it is likely to happen again. And next time two chips may have more differences than just one .wps reg bit.
As an upstream project, we maintain all the chips (and older too) and removing the chip definition is something extremely rare (to the extent that I have never seen this happening).
There are lots of users, and you never know which chips people are using.
Specifically to your customer situation, if the customer has a fork of flashrom, they can introduce a local list of chips to ignore, and add old models there. This way they don't need to change automatic test flow, and also it's a future-proof solution as any more old chips like that can be added to the list.
In terms of how hard it is to implement, Chrome OS flashrom is also open source, and they implemented this solution, so the code can be used as an inspiration. If you are interested, I can try to find links to relevant code.
I don't know how your communication with customer is set up, but if it is fine, you are welcome to share with them the link to this patch (so that they can see the discussion), and you can even add them to this patch (if there is an engineer from customer side who can create a Gerrit account).
What do you think about it?
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Change subject: fmap: Update major/minor version check
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/flashrom/+/79060/comment/873dd0ba_d6b35c69 :
PS2, Line 9: It's not valid to separately check the major and minor versions. The
: proper minor check would be something like:
:
: if (fmap->ver_major == FMAP_VER_MAJOR &&
: fmap->ver_minor > FMAP_VER_MINOR)
Brian, I like this idea! Maybe you can move the code from commit message into the code? :)
I looked into the chromiumos patch you linked, it still checks both major and minor versions.
The diff I see is that the check is more strict (both major and minor version expected to be exact equal) while initial fmap.c checks that the versions are not greater than.
I can agree to make the check more strict, but I don't see why checking minor version has to be dropped, I think it can stay?
I admit I haven't looked into cbfstool code, is there a way you can link a relevant piece? (if you think it's useful. if not then not)
Patchset:
PS2:
> Hi Anastasia: […]
Sure, I am having a look! I added one comment.
I didn't realise this patch is hanging without attention, sorry
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Change subject: flashrom_tester: Fix partial_lock_test on libflashrom
......................................................................
Patch Set 4: Code-Review+2
(2 comments)
Patchset:
PS3:
> Ed, Evan, thank you so much for reviews! Could you please vote on the patch?
Alright, it seems you are busy at the moment.
File util/flashrom_tester/flashrom/src/cmd.rs:
https://review.coreboot.org/c/flashrom/+/79304/comment/fb09e840_e2c6053e :
PS3, Line 301: // TODO
> From a syntax perspective: […]
Thank you for detailed explanation, I appreciate so much!
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Change subject: fmap: Update major/minor version check
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
Hi Anastasia:
Could you help check if this is okay to submit?
Thanks!
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Change subject: flashrom_tester: Fix partial_lock_test on libflashrom
......................................................................
Patch Set 4:
(1 comment)
File util/flashrom_tester/flashrom/src/cmd.rs:
https://review.coreboot.org/c/flashrom/+/79304/comment/96ba8561_f2faa87d :
PS3, Line 301: // TODO
From a syntax perspective:
In Rust, `pub trait Flashrom` is an interface that defines method signatures, such as `write_from_file()` and `wp_range()`.
We have two structs, `pub struct FlashromLib` (from `util/flashrom_tester/flashrom/src/flashromlib.rs`) and `pub struct FlashromCmd` (from `util/flashrom_tester/flashrom/src/cmd.rs`), that implement the `Flashrom` trait. This enables polymorphism.
To prevent runtime errors, both `FlashromLib` and `FlashromCmd` must implement the `fn set_flags()` method from the `Flashrom` trait.
---
From the `flashrom_tester`'s perspective:
flashrom_tester supports two execution scenarios: "cmd" and "lib".
lib: In this scenario, a `flashrom_lib` instance is created at the beginning of the test. Its constructor (link to constructor: [gerrit]( https://review.coreboot.org/c/flashrom/+/79304/4/util/flashrom_tester/src/t… should set default flags that will be used by all commands with `set_flags()`.
cmd: Methods are interpreted as sequences of flashrom commands. Each command resets flags to default values (link to cli_classic: [github](https://github.com/flashrom/flashrom/blob/main/cli_classic.c#L1226)). Therefore, no action is needed within set_flags().
---
> I am not sure whether we get votes from Ed and Evan, maybe not, I will try to finish review by myself, so that's why I am having questions :)
Thanks! I am not deeply familiar with `flashrom_tester` or Rust either, but I'll try to answer all the further questions.
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Change subject: Add Idaville platform into chipset enable list and add update IRC region support
......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
> Hi Anastasia […]
Hi Anastasia
Reference documentation
618610_Intel_Xeon_Processor_Family_D-2700_EDSVol_1_Rev2p0.pdf - Section 41.1.6 Firmware Components
631913_Xeon_D-1700_2700_SPI_PG_Rev2_0.pdf - Section 4.3 Region Access Control
intel-sps-5-0-me-bios-interface-575642-rev1-8.pdf - 4.15.2.9 Dual iRC Update Support
iRC – Intelligent Reset Controller
iRC is a regional firmware for the Intel BIOS Firmware for Mehlow, Idaville and Jacobsville platforms.
iRC is stored in Region 13 which is split in two even sections: active image and backup image. On startup higher version is chosen to by applied.
This means that the status of the two region is not fixed. The higher version area will become the active image and the other region will become the backup image.
According to #631913 SPI programming guide and ME 5.0 spec description, in addition to giving Region 13 read and write permissions, updating iRC must also unlock iRC through Host ME Region Flash Protection Override (HMRFPO) HECI commands, otherwise iRC will not be writable.
According to iRC Update Flow, the HMRFPO command will only unlock the backup image and can only update the backup image each time. The active image cannot be written.
So for iRC, the submitted changes are divided into the following two parts:
1. Trigger HMRFPO command before updating iRC. HMRFPO command needs to be executed by BIOS Firmware, and flashrom needs to cooperate with BIOS to trigger the command to unlock before updating.
2. Skip errors caused by active image writing failure and continue updating other regions. Since the active image is not writable, during the erasing, writing and verification processes, an error will occur in the active image, causing the flashrom to end its operation.
The revised commit has put the changes to the erase and write parts into ich_hwseq_wait_for_cycle_complete() of ichspi.c.
But the changes to the validation part are still in flashrom.c's compare_range(), which doesn't seem to be transferable to ichspi.c.
Thanks
KevinYu
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Change subject: doc: Add docs how to add and update test status of flashchips
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Patch Set 4: Code-Review+1
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Change subject: doc: Add docs how to add and update test status of flashchips
......................................................................
Patch Set 4:
(1 comment)
File doc/contrib_howtos/how_to_add_new_chip.rst:
https://review.coreboot.org/c/flashrom/+/80205/comment/b229119a_4e6d03ad :
PS3, Line 86: abc
> nit: replace with `alphabetic`?
Done
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