Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/25047
to look at the new patch set (#5).
Change subject: Add support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Add support for Atmel / Adesto AT25SF041 SPI flash chip
probe/erase/read/write/verify hardware-tests were done.
Change-Id: I0be930ff2258300508398e12fbe5abe10400fea2
Signed-off-by: Julian von Mendel <git(a)jinvent.de>
Signed-off-by: jvm <git(a)jinvent.de>
---
M flashchips.c
M flashchips.h
2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/47/25047/5
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/25047 )
Change subject: Add support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Patch Set 4:
(3 comments)
Before I continue the review: Is this really the version you tested?
You said something about a copy of AT25DF041A on IRC, but this looks
like a copy of AT26DF041 which doesn't seem to make much sense.
https://review.coreboot.org/#/c/25047/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/25047/4//COMMIT_MSG@9
PS4, Line 9: Reasonably certain this is working due to erase/read/write hardware-tests in a setup in which the flash content contained a running FPGA program. Meaningful content was stored on the chip beforehand. I read a.rom, erased, observed the FPGA dead, read b.rom, wrote back a.rom, observed the FPGA alive again. I verified b.rom in a hex editor contained 0xff only.
: The FPGA data used only a small portion of the address space, so I also wrote out a file with specific 3 bytes in the first and last memory page. All flashrom verify cycles passed.
Line length limit is 72 chars. I also don't see a reason for the
whole story. Just stating that probe/read/erase/write was tested
should be enough.
https://review.coreboot.org/#/c/25047/4/flashchips.c
File flashchips.c:
https://review.coreboot.org/#/c/25047/4/flashchips.c@2194
PS4, Line 2194: .block_erase = spi_block_erase_81,
Can't find anything about it in the datasheet.
https://review.coreboot.org/#/c/25047/4/flashchips.c@2197
PS4, Line 2197: .block_erase = spi_block_erase_50,
0x50 is EWSR (enable write status register)
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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/25047
to look at the new patch set (#4).
Change subject: Add support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Add support for Atmel / Adesto AT25SF041 SPI flash chip
Reasonably certain this is working due to erase/read/write hardware-tests in a setup in which the flash content contained a running FPGA program. Meaningful content was stored on the chip beforehand. I read a.rom, erased, observed the FPGA dead, read b.rom, wrote back a.rom, observed the FPGA alive again. I verified b.rom in a hex editor contained 0xff only.
The FPGA data used only a small portion of the address space, so I also wrote out a file with specific 3 bytes in the first and last memory page. All flashrom verify cycles passed.
Change-Id: I0be930ff2258300508398e12fbe5abe10400fea2
Signed-off-by: Julian von Mendel <git(a)jinvent.de>
Signed-off-by: jvm <git(a)jinvent.de>
---
M flashchips.c
M flashchips.h
2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/47/25047/4
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Julian von Mendel has removed a vote on this change.
Change subject: Support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Removed Code-Review+1 by Julian von Mendel <git(a)jinvent.de>
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/25047 )
Change subject: Support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Patch Set 3:
I think, the commit authors normally doesn’t score their own changes.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/23840 )
Change subject: Add "gingerly" flashing mode for the unreliable ISP environments
......................................................................
Patch Set 2:
> However, even with such a dangerous boards in the existence, ISP is
> still much safer than desoldering a flash chip without an experienced
> steady hand - that's why I believe the advanced modes for ISP flashing,
> be it that "gingerly" mode or any other future inventions, have a right
> to exist
No need to argue about that. It just has to be done right. And in a way
that doesn't encourage users to do stupid things.
>>>> And that is where the problems start... if it can fail,
>>>> we have to handle the failure correctly, otherwise
>>>> flashrom (in its current implementation) would probably
>>>> fall back to erase the whole chip and make things worse.
>>>
>>> If there is a timeout: we could just print some error message and
>>> shutdown the flashrom, then it shouldn't do anything else... also,
>>> why would it try to erase the whole chip if we didn't specify such
>>> an operation?
>>
>> Flashrom defaults to try another erase function if one fails,
>> finally using one that erases the whole chip. Can be handled
>> more gracefully ofc, just something that we have to keep in
>> mind.
>>
>
> Perhaps there should be a way to just exit a flashrom with some message
> without trying any other erase functions. Maybe by adding a new return
> value to the erase functions ( perhaps "2" or "-2" if there is already
> "1" or "-1" code in the failure case ) and adjusting the flashrom
> algorithm to act accordingly if such a return value has been accepted
> from erase function
Yes, there is already a distinction in return values. One just has to
choose the right one. Maybe it is already safe, I just wanted to make
sure we don't forget about it ;)
>>> Also, if we'd introduce a timeout - it shouldn't be hardcoded. In
>>> example: if I'd hardcode it to 5 seconds - it will block a way for
>>> the boards whose chip is available for 1 second per each 10 seconds;
>>> hardcode to 15 seconds - blocks those which are 1sec/20sec available,
>>> and so on
>>>
>>> Most likely we'll have to introduce a new flag "-t | --timeout
>>> <seconds>" ("t" is also not occupied) but lets' have more discussions
>>> to clarify our further steps
>>
>> I would prefer a static timeout, doesn't have to be a small one.
>> For instance 60s, then bail out. It's not that bad to wait 1min
>> but if single hunks take more than 60s, nobody would have the
>> patience to wait for the full run anyway.
>>
>
> Is it possible that there are some boards with a lengthy
> available/unavailable durations, like " 70 seconds unavailable / 30
> seconds available " ? If yes, the full run would still could take a
> reasonably small time despite the long wait between each two groups of
> many successful attempts
Anything is possible with a broken hardware setup... how about we
start with a static timeout and discuss an option for it in a follow-
up commit?
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Julian von Mendel has posted comments on this change. ( https://review.coreboot.org/25047 )
Change subject: Support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Patch Set 3: Code-Review+1
I did function tests with read/write/erase, no systematic flash performance tests or similar.
I had a Pi connected to the SPI flash chip, that contained FPGA configuration data (that were already on the chip). I read the data, erased, read that as well, confirmed that both images made sense in a hex editor and that the FPGA did no longer configure. I wrote back the original image and the FPGA worked as it did before. No errors during flashrom verify. (Possible flaw in that test: Only a small portion of the address space was filled with non-zero data.)
Sorry about the comments in the .c file, I am not sure about these (they were copied from AT26DF041).
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/25047 )
Change subject: Support for Atmel / Adesto AT25SF041 SPI flash chip
......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/#/c/25047/3//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/25047/3//COMMIT_MSG@7
PS3, Line 7: Support for Atmel / Adesto AT25SF041 SPI flash chip
Maybe:
> Add support for …
https://review.coreboot.org/#/c/25047/3//COMMIT_MSG@8
PS3, Line 8:
Tested how?
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