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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/58479 )
Change subject: libflashrom,writeprotect: add flashrom_wp_{read,write}_chip_config()
......................................................................
Patch Set 22:
(1 comment)
File libflashrom.h:
https://review.coreboot.org/c/flashrom/+/58479/comment/76502ee8_0a2e8666
PS11, Line 4: 2010
> I think the best option is probably to just keep the first copyright year, since we also have git fo […]
Sounds about right. Generally it's the year of the _first_ publication of
an original work, AFAIK. Anything based on this work would still keep the
original date.
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Sergii Dmytruk has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/60231 )
Change subject: writeprotect: add WPS bit and set it to zero
......................................................................
writeprotect: add WPS bit and set it to zero
Handle WPS by always setting it to zero until proper support for it is
implemented.
Change-Id: I2c26ec65d64a3b6fb1f1a73690bc771415db2744
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M writeprotect.c
2 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/31/60231/1
diff --git a/flash.h b/flash.h
index 16a31ed..a49e615 100644
--- a/flash.h
+++ b/flash.h
@@ -315,6 +315,7 @@
struct reg_bit_info tb;
struct reg_bit_info sec;
struct reg_bit_info cmp;
+ struct reg_bit_info wps; /* Write Protect Selection (per sector protection when set) */
} reg_bits;
wp_range_decode_fn_t decode_range;
diff --git a/writeprotect.c b/writeprotect.c
index bcd0657..39c782f 100644
--- a/writeprotect.c
+++ b/writeprotect.c
@@ -79,6 +79,7 @@
ret |= read_reg_bit(flash, bits->tb, &cfg->tb, &cfg->tb_bit_present);
ret |= read_reg_bit(flash, bits->sec, &cfg->sec, &cfg->sec_bit_present);
ret |= read_reg_bit(flash, bits->cmp, &cfg->cmp, &cfg->cmp_bit_present);
+ /* Note: WPS bit isn't read here, because it's not part of any range. */
for(size_t i = 0; bits->bp[i].reg != INVALID_REG; i++) {
ret |= read_reg_bit(flash, bits->bp[i], &cfg->bp[i], &tmp);
@@ -130,6 +131,8 @@
set_reg_bit(reg_values, write_masks, bits->tb, cfg->tb);
set_reg_bit(reg_values, write_masks, bits->sec, cfg->sec);
set_reg_bit(reg_values, write_masks, bits->cmp, cfg->cmp);
+ /* Note: always setting WPS bit to zero until its fully supported. */
+ set_reg_bit(reg_values, write_masks, bits->wps, 0);
/* Write each register */
for (enum flash_reg reg = INVALID_REG; reg < MAX_REGISTERS; reg++) {
@@ -262,6 +265,8 @@
if (can_write_bit(bits->cmp))
range_bits[bit_count++] = &cfg.cmp;
+ /* TODO: take WPS bit into account. */
+
/* Enumerate all values the range bits can take and find the range
* associated with each one. */
*count = (1 << bit_count);
--
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Hello build bot (Jenkins), Nico Huber, Angel Pons,
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Change subject: [RFC][OTP] spi25_statusreg: support reading/writing security register
......................................................................
[RFC][OTP] spi25_statusreg: support reading/writing security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing corresponding write
command with no data just sets OTP bit to 1 automatically.
No WREN is necessary, but at least some datasheets indicate BUSY state
after write command.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 59 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/59709/13
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Change subject: dummyflasher: add SR2 and SR3 emulation harness
......................................................................
dummyflasher: add SR2 and SR3 emulation harness
Prepare everything for emulating SR2 and SR3 for chips that have it.
This is needed for accessing SRP1 and WPS bits which are involved in
write protection. The emulated register doesn't affect anything yet
and will be tested by write-protection tests.
Change-Id: I177ae3f068f03380f5b3941d9996a07205672e59
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M dummyflasher.c
M flashrom.8.tmpl
2 files changed, 101 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/72/59072/21
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Change subject: flashchips: enable write-protection for W25Q{64,128}.V
......................................................................
flashchips: enable write-protection for W25Q{64,128}.V
Configuration for W25Q64 was tested on hardware (W25Q64FV).
Emulation of W25Q128 in dummyflasher will be extended to support WP.
Haven't tested this one on hardware, but it's the same configuration as
for W25Q64 except that it has WPS.
W25Q64.V chip was split into W25Q64BV/W25Q64CV/W25Q64FV (no SR3 and WPS)
and W25Q64JV (SR3 and WPS).
Change-Id: Iccb69a8d3a0dd2192e2c938caddaf07b1889ed35
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
M flashchips.c
1 file changed, 75 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/71/59071/17
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Hello build bot (Jenkins), Nico Huber, Angel Pons, Anastasia Klimchuk, Nikolai Artemiev,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#21).
Change subject: dummyflasher: emulate SR2 for W25Q128FV
......................................................................
dummyflasher: emulate SR2 for W25Q128FV
Enable emulation of SR2 for W25Q128FV and provide logic for updating
it (mask of read-only bits that can't be set from outside).
W25Q128FV has three status registers, but no plans to use the third
one yet.
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---
M dummyflasher.c
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git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/59073/21
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Change subject: tests: test write protection
......................................................................
tests: test write protection
Tests both WP implementation and its emulation in dummy programmer.
Change-Id: I49af7f6d173eb4c56c22d80b01a473b8c499c0f8
Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>
---
A tests/chip_wp.c
M tests/meson.build
M tests/tests.c
M tests/tests.h
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